LCIII EPROM?

[max1zzz]

It's from a very uncompleted schematic I was drawing form my repro PCB, I got about half way through then got distracted and never got back to it, one day I'll get around to completing it.....

 

[frontein1]

It's from a very uncompleted schematic I was drawing form my repro PCB, I got about half way through then got distracted and never got back to it, one day I'll get around to completing it.....

OK but wow, this is awesome!! Thank you for sharing.

 

[dougg3]

That connector is actually +12V, A22 and /WR on the SCSI/SCC

Ah, nice catch! Looks like the Bomarc schematic has an error:



I confirmed it's A22 on one of my LC IIIs as well, thanks for the correction!

What you found about A22 makes even more sense and is probably more evidence that it has to do with rewritable ROMs. It makes sense they wouldn't need ground on that connector because you get it from the ROM sockets anyway. A22 is probably being used as an additional qualifier for /WE, to avoid sending SCSI/SCC write cycles to the flash chips. Whatever board was supposed to plug into J11, probably has a PLD or logic gates or whatever to limit it so it only sends /WE out to the flash chips if A22 is high.

There are several table entries in the Flasher app that contain the LC III's gestalt ID. Most of them are shared with the Quadras, and use a base address of 0x40800000 for ROM reads and 0x40400000 for ROM writes. That lines up perfectly with why A22 would be in that connector. A22 would be high during writes.

I have my doubts about whether those Quadra table entries will work out of the box on the LC III because of 68030 vs 68040 differences in the transparent translation registers, but it might be interesting to play with it.

There is also an additional entry that only has the LC III's gestalt ID and uses 0x40200000 for writes instead, which would be A21. A21 could be grabbed directly from one of the two extra pins in the ROM socket if that table entry was being used, at the expense of taking away half of the usable ROM capacity.

On annother side note, U25 appears to be a footprint for a 27C512 type eprom, I have always wondered what that was there for but I haven't ever seen a picture of a board with that populated

Great question. Its output enable line is going to Sonora pin 110 according to the Bomarc schematics anyway. I wonder if @Arbee knows what that's about?

 

[joevt]

LC III's gestalt ID is 27? aka gestaltVail?
The flasher has these 5 options for that gestalt ID:
- Intel 28F020, write: 40400000 read: 40800000, 2 banks, 1 MiB each, not PDS (040, also works on Quadra)
- AMD 28F020, write: 40400000, read: 40800000, 2 banks, 1 MiB each, not PDS (040, also works on Quadra)
- Intel 28F020, write: 40400000 read: 40800000, 1 banks, 1 MiB each, not PDS (040, also works on Quadra)
- AMD 28F020, write: 40400000, read: 40800000, 1 banks, 1 MiB each, not PDS (040, also works on Quadra)
- Intel 28F020, write: 40200000 read: 40800000, 1 banks, 1 MiB each, not PDS (030, only for Vail)
These 5 options don't have a write enable/disable function like other motherboards do (usually a bit of a register that controls /WE)
They have an enable translation function which switches the MMU mode to 32bit.