LCIII EPROM?
- Thread starter frontein1
- Start date
This research (authored by a user here!) helped me figure out which ROMs were compatible with my IIcx and IIci, and gave enough introductory info to help me replace my failed mask ROMs with cheaper flash ones... After a bit more help from other users here, who alerted me to the obvious but easily-solved pitfall I forgot about: Common flash chips like the SST39SF010 need the Write Enable pin to be high when in the Mac, to enable reading. Other than that, they're perfect.
Nice, have fun!
consider investing in an EPROM eraser too!
protip: the phone sanitizers with UV bulbs (not LEDs) work VERY well.
they can also be had fairly cheaply and are generally higher quality than the generic "eprom eraser" deathtraps you can get on amazon and such.
I went with the GQ-4X4 from MCUMall. Also with the appropriate adapter and UV eraser. I'll report back on how that bundle works.
Interestingly, I took a closer look at the board, and I noticed that the ROM sockets are actually 42-pin each even though the ICs being used are 40-pin. I pulled up the Apple Developer Notes and Bomarc schematics. I am wondering if these are tied to additional address lines, and if so, perhaps I could expand the ROM to 4MB with room for a built-in ROM Disk.
They are. They go to A20 and A21. I haven't tried it myself, but it should work. I'm not sure if you would need to do any MMU reconfig like what was required for the Quadras, but it should be possible to get 4 MB of ROM in the LC III.
Looks like I've identified my MARCHintosh project for this year!
If it works, I may do this for my overclocked LC III
LCIII ROM patched and 3MB ROM disk embedded. Happy MARCHintosh! I know, a bit late.... I would have made it in time, but I got a batch of really bad M27C160s from China. So I scrapped them and had to buy and then wait for a new batch.
- Two M27C160 EPROMs: 1024K x 16 = 2MB each (4MB total). ROM = 1MB, DISK = 3MB. 42-pin EPROMs to take advantage of all address lines.
- Patched the Sonora tables to support a 4MB ROM in 32-bit mode (thanks @dougg3 for pointing me towards Sonora). I was able to boot to R in both 24-bit and 32-bit mode, but I don't trust the 24-bit option quite yet.
- Using an older version of my driver, what I call v0.90. This pre-dates the usage of the splash screen as I didn't want to test toolbox routines until I knew that this was working.
- Other ROM patches include: Disable RAM test, disable ROM checksum, usual changes to auto-open and optionally boot from ROMDISK driver. Used free resource at offset 60080 for this driver.
- Included ZIP file has the Big Endian HI and LO files ready for programming. Again be advised that I haven't done a lot of testing quite yet, especially as it pertains to 24-bit mode. In time I will run in the much more current v1.1 driver I am about done with. This includes full support for FC8, including caching the FC8b for faster access.
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Nicely done!
On a slightly unrelated tangent, I'd bet money that unpopulated connector J11 has something to do with in-system programming of the ROM. It has GND, +12V (VPP), and a pin that involves write cycles to the Z85C80 SCSI/serial controller. That third pin could probably also act as the /WE for ROM chips, especially knowing that the ROM chips require special unlock sequences to actually start being programmed. In other words, SCSI/serial write cycles would likely be harmless to the ROM.
The Flasher app supports the LC III, so that's more evidence that it was likely used for this back in the day. The table entry for the LC III expects to see four Intel 28F020 chips for a total of 1 MB of ROM. My guess is there was some kind of adapter board that plugged into the two ROM sockets and J11, and provided four ROM chip sockets (or maybe a 64-pin ROM SIMM socket).
That would potentially be an interesting project. The Flasher app could probably be hacked to do in-system programming of newer, larger chips too.
On a slightly unrelated tangent, I'd bet money that unpopulated connector J11 has something to do with in-system programming of the ROM. It has GND, +12V (VPP), and a pin that involves write cycles to the Z85C80 SCSI/serial controller. That third pin could probably also act as the /WE for ROM chips, especially knowing that the ROM chips require special unlock sequences to actually start being programmed. In other words, SCSI/serial write cycles would likely be harmless to the ROM.
The Flasher app supports the LC III, so that's more evidence that it was likely used for this back in the day. The table entry for the LC III expects to see four Intel 28F020 chips for a total of 1 MB of ROM. My guess is there was some kind of adapter board that plugged into the two ROM sockets and J11, and provided four ROM chip sockets (or maybe a 64-pin ROM SIMM socket).
That would potentially be an interesting project. The Flasher app could probably be hacked to do in-system programming of newer, larger chips too.
