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Help! Attempting SE/30 cpu socket to PowerCache pinout
- Thread starter IamSpartacus
- Start date
tt - just probe the soldered edges of the resistors to see which pin they go to. If one side maps to multiple pins with zero resistance, that's likely ground or 5V.
At this point there's no way for us to find out if there is anything beneath the socket, aside from x-raying it. I'll chance it.
At this point there's no way for us to find out if there is anything beneath the socket, aside from x-raying it. I'll chance it.
Oh, and please do check the red pins too, just to be safe. I'm putting my only SE/30 at risk
Aha ... I see someone else has noticed the utter simplicity of the IIcx adapter as well 
Eeexcellent.
Everyone is clear that this adapter goes into the '030 CPU socket, not the PDS, correct?
IamSpartacus, I note in your OP you say:
Eeexcellent.Everyone is clear that this adapter goes into the '030 CPU socket, not the PDS, correct?
BRILLIANT!
That is fantastic news. What accelerators were you able to use it with? Were you able to reassemble the SE/30 with the adapter & accelerator in place?
IamSpartacus, I note in your OP you say:
Is that still the plan, or are you now intending to construct a PCB?
You'd best move to the PCB setup Bunsen suggested soon after completing your debugged, proof of concept, Wire Wrap(?) ProtoBoard.
That puppy is gonna throw off enough RFI that it might actually interfere with your PowerCache/SE/30 MoBo under testing!!!! 8-o
If it's to be a straight wiring deal, you might need cable drivers at the CPU end if the wires get long enough. (ease of installation)
I'd suggest using shielded ribbon cable with alternate ground lines, but that would interfere with keeping every wire of equal length for timing.
Is there a good, individually shielded, wire for use in prototyping situations like this?
Keep in mind, I'm a worrywart when it comes to timing, crosstalk, RFI etc. :I
That puppy is gonna throw off enough RFI that it might actually interfere with your PowerCache/SE/30 MoBo under testing!!!! 8-o
If it's to be a straight wiring deal, you might need cable drivers at the CPU end if the wires get long enough. (ease of installation)
I'd suggest using shielded ribbon cable with alternate ground lines, but that would interfere with keeping every wire of equal length for timing.
Is there a good, individually shielded, wire for use in prototyping situations like this?
Keep in mind, I'm a worrywart when it comes to timing, crosstalk, RFI etc. :I
Let me clarify, we've mapped all 86 visible leads on the board. There's still the matter of the caps and resistors.
The plan is still to make a wire harness. I'm putting the Turbo 040 where the HD used to be, so I'll need the connector to be flexible.
Trash80- My first impulse is to use wire pulled from a bundled U2W SCSI cable. The length should be about equal to the leads in the iicx adapter, so I'm not too worried about that. If there's too much RF I'll wrap the wire bundle in foil or something.
I'm also thinking of wiring all the 5V and GND pins of the Turbo040 directly to a hard drive connector via nice fat wires. Hopefully this will remove the need for those capacitors the IIcx adapter has.
While we're at this, has anybody got one of those ludicrously expensive Japanese PDS adapters for the SE/30? :?:
I've been poking around the IIsi Docs and for the life of me, I can't figure out why that infernal PAL is needed for that design. Does it enable an additional PDS PseudoSlot from the existing number of PseudoSlots available?
How many PseudoSlots are already accessible on the SE/30 anyway? :?:
Rhetorical question, I can look it up when I have time, but a /30 hacker will probably have an explanation of the logical function of that card as well as the SlotInfo specs to go with it.
I've been poking around the IIsi Docs and for the life of me, I can't figure out why that infernal PAL is needed for that design. Does it enable an additional PDS PseudoSlot from the existing number of PseudoSlots available?
How many PseudoSlots are already accessible on the SE/30 anyway? :?:
Rhetorical question, I can look it up when I have time, but a /30 hacker will probably have an explanation of the logical function of that card as well as the SlotInfo specs to go with it.
My understanding is the PAL is needed to convert the PDS slot to a IIci cache slot. Maybe it also handles the PDS pass-through functionality for the additional SE/30 PDS slot.
Maybe the Artmix adapter or Daystar adapter with PAL could be redesigned to allow for a IIci cache slot and two PDS slots. If you had a low-profile SCSI-CF drive installed, then there would probably be room. If you are looking at the Artmix adapter, the extra PDS slot would be parallel to the IIci cache slot.
Maybe the Artmix adapter or Daystar adapter with PAL could be redesigned to allow for a IIci cache slot and two PDS slots. If you had a low-profile SCSI-CF drive installed, then there would probably be room. If you are looking at the Artmix adapter, the extra PDS slot would be parallel to the IIci cache slot.
If the Artmix Adapter's PAL is for adapting the SE/30's PDS Slot to a IIci Cache Slot Card, you shouldn't need it at all to address as many SE/30 or IIsi cards as the SE/30's address map can handle.
The SE/30's PDS "Slot" is the equivalent of an extensible, pre-VESA, local bus slot on a PC. You can stick as many cards on that bus as the PC's BIOS or the Mac's ROM will allow in its memory mapping scheme. That's why you can have IIsi & SE/30 Cards that daisy-chain off each other. These are constrained only by provision for the daisy-chaining connectors, address compatibility jumper setting availability, accessible cubic within the Mac and the number of PseudoSlot addresses available in the ROM's memory mapping.
Three PseudoSlot addresses are available to the IIsi and :?: are available to the SE/30. A PAL should be unnecessary for a similar adapter if it is ONLY moving the connections around to spaces where cubic is available to max out the SE/30's PseudoSlot/PDS Card Addressing allotment . . .
. . . as would be the case under consideration, with an '030 Socket conversion for the PowerCache . . .
. . . or so I understand the situation!
)
The SE/30's PDS "Slot" is the equivalent of an extensible, pre-VESA, local bus slot on a PC. You can stick as many cards on that bus as the PC's BIOS or the Mac's ROM will allow in its memory mapping scheme. That's why you can have IIsi & SE/30 Cards that daisy-chain off each other. These are constrained only by provision for the daisy-chaining connectors, address compatibility jumper setting availability, accessible cubic within the Mac and the number of PseudoSlot addresses available in the ROM's memory mapping.
Three PseudoSlot addresses are available to the IIsi and :?: are available to the SE/30. A PAL should be unnecessary for a similar adapter if it is ONLY moving the connections around to spaces where cubic is available to max out the SE/30's PseudoSlot/PDS Card Addressing allotment . . .
. . . as would be the case under consideration, with an '030 Socket conversion for the PowerCache . . .
. . . or so I understand the situation!
)
So are the PDS pass-through slots in series? http://www.biwa.ne.jp/~shamada/fullmac/se30_minitowerEng.html indicates 6 addresses. Maybe the PAL is tapping into the PDS and switching-off between sending instructions to the IIci cache slot and passing them through to the rest of the PDS chain?
My point is, I am guessing the SE/30 PDS slot has more going on than just routing lines to the CPU, and that's why to get it to a state the PowerCache can handle, it needs to involve some logic.
My point is, I am guessing the SE/30 PDS slot has more going on than just routing lines to the CPU, and that's why to get it to a state the PowerCache can handle, it needs to involve some logic.
I don't read it that way at all, the SE/30, according to that site and assuming they're using the SE/30's native ROM, has 5 available addressable PseudoSlot IDs.
If the Artmix Adapter places the PowerCache at one specific slot location inline (in series) with the PAL and its theoretical adaptation of the SE/30's straight up 68030 local bus to a IIci Cache Slot config, that PAL would be totally unnecessary. A similar adapter should be workable for moving as many as four other cards about the internal cubic of the SE/30. If, with the total replacement (?) of the 68030 with the PowerCache in an '030 socket adapter, it winds up at the MoBo's address $E, you'd have all five PseudoSlot addresses available for "Stock" or "adapted" PDS Cards.
The CPU controls which Card is addressed with interrupts and address calls to whichever Card IT decides to address, the adapters extending the bus should have nothing to do with it at all!
Very interesting, indeed! }
If the Artmix Adapter places the PowerCache at one specific slot location inline (in series) with the PAL and its theoretical adaptation of the SE/30's straight up 68030 local bus to a IIci Cache Slot config, that PAL would be totally unnecessary. A similar adapter should be workable for moving as many as four other cards about the internal cubic of the SE/30. If, with the total replacement (?) of the 68030 with the PowerCache in an '030 socket adapter, it winds up at the MoBo's address $E, you'd have all five PseudoSlot addresses available for "Stock" or "adapted" PDS Cards.
The CPU controls which Card is addressed with interrupts and address calls to whichever Card IT decides to address, the adapters extending the bus should have nothing to do with it at all!
Very interesting, indeed! }
I probed the pins in red, and it seems like they aren't connected to the pins at the cache slot.
I probed the resistors:
R1: 678 ohms
R2: 390 ohms
R3: 678 ohms
The pins below are ones I happened to find first, and then I started poking other ones that seem related.
R1: F11 short and other pins labeled +5, F12 390 ohms
R2: L6 short and other pins labeled +5
R3: L6 short and other pins labeled +5
There's also a C3 and a C9 underneath the male-to-male socket adapter. I used the Daystar PGA puller to get that part off.
C3: H3 & GND
C9: F2 & GND
I don't really understand what should be connected to what for resistors and capacitors, like should the resistors be in series with links between the cache and cpu sockets? Maybe a hypothetical schematic would help me understand how to probe it more efficiently.
I probed the resistors:
R1: 678 ohms
R2: 390 ohms
R3: 678 ohms
The pins below are ones I happened to find first, and then I started poking other ones that seem related.
R1: F11 short and other pins labeled +5, F12 390 ohms
R2: L6 short and other pins labeled +5
R3: L6 short and other pins labeled +5
There's also a C3 and a C9 underneath the male-to-male socket adapter. I used the Daystar PGA puller to get that part off.
C3: H3 & GND
C9: F2 & GND
I don't really understand what should be connected to what for resistors and capacitors, like should the resistors be in series with links between the cache and cpu sockets? Maybe a hypothetical schematic would help me understand how to probe it more efficiently.
Hmm, I don't quite get it either. An x-ray would be pretty useful right now. Can you verify F12? I think I should have made that one yellow instead of green.
N00B question: what's a cable driver?
Consult gamba's SE/30 corner, or the Minitower SE/30 site. One or t'other of those pages has that info, I believe.
Well ... no. As the above two sites demonstrate. It's strictly for the IIci-PDS Daystar accelerators.
They're not physical slots, they're pseudo-slot addresses. And the cards themselves select their address (as I recall), not the Mac, nor any adapter. Most cards are hardwired to one address (or ID), some can be reset with jumpers. The physical arrangement of cards matters not a whit, except insofar as which cards have a passthrough PDS, and physical space issues.
I've managed to get my hands on a IICX adapter, and have completed the pinout page. In theory, this diagram could be used to wire up an adapter between Daystar accelerators and any 68030 socket.
http://hiddenkingdom.net/temp/pinout.htm
My only remaining question is this: the card has 8 small capacitors arranged in parallel. All of them bridge +5VDC and GND. This puzzles me. Can anyone with some EE experience explain this? Why use 8 small caps rather than 1 large cap?
Now to build one and see if it works...
http://hiddenkingdom.net/temp/pinout.htm
My only remaining question is this: the card has 8 small capacitors arranged in parallel. All of them bridge +5VDC and GND. This puzzles me. Can anyone with some EE experience explain this? Why use 8 small caps rather than 1 large cap?
Now to build one and see if it works...
In general, smaller capacity capacitors (lower farads) react more quickly. So, let's say your supply is 5V and you can't tolerate a low voltage condition which lasts for more than 10 ns. So you need a capacitor with a small enough rating that it can react and supply stored charge to bring the voltage back up in less than 10 ns.
However, you may need to supply 30 watts of power at 5V = 6 amps. So you need enough capacitors that they can supply 6 amps at the difference in voltage which might occur. So you use a bunch of them, until they have enough charge capacity to supply 6 amps.
But these little caps are going to be depleted really quickly. They may react quickly, but they don't store much total charge. They may react within 10 ns and be exhausted by 50 ns. So if you want to be able to bridge a shortfall which lasts 1 millisecond, you might put in a much larger (in u Farads) capacitor.
This capacitor will react more slowly, but that's okay, the little guys have it covered during the initial period. By the time the little guys are out of spare juice, the big guy has started supplying current and is now supporting the voltage and being a (relatively) big capacitor, it can last much longer than the little guys.
In practice, there will be a bunch of little chip ceramic capacitors in the 1,000 - 100,000 picofarad (1 - 100 nanofarad) range (at least on newer faster stuff), some electrolytic or tantalum caps in the 10 - 50 uF range, and a few bigger guys in the 200 - 500 uF range.
In practice, I doubt that the adapter board really needs the caps. There are decoupling caps on the logic board around the CPU socket. There are decoupling caps on the Daystar upgrade board. It seems unlikely that they're really essential on the adapter board as well, but Daystar put a lot of engineering into their stuff. They may have added a little overcapacity.
Trag- that's plausible. I'm going to experiment with variable numbers of caps to see if it makes a difference. I'll be using a Turbo040, so if anything has power requirements enough for this to matter, that's it.
tt- the project is happening, but on hold due to obligatory holiday vacationing. It's going to be mostly wires, with a small pcb to unify the 5V and GND wires, and to hold any caps I'll use. Expect progress in january
tt- the project is happening, but on hold due to obligatory holiday vacationing. It's going to be mostly wires, with a small pcb to unify the 5V and GND wires, and to hold any caps I'll use. Expect progress in january
