Macintosh 68060 Redux

A Quadra 650 should theoretically be somewhere between 30-40mb/s of memory bandwidth with line transfers. Scaling for clockspeed that'd give BFG 58 mb/s of bandwidth with the full speed bus @ 64mhz, seems to correspond nicely with the observed results of BFG managing ~2x blockmove performance.

That "slow" half speed L2 cache can supply data at 85 MB/s with similar latency to what BFG's RAM timings probably are; it makes sense that the cache would bring the read-heavy Tree, Sort and Search benchmarks to a similar range as the BFG. Real world performance of the cache is going to depend on data locality, though, cache thrashing wrecks performance.

If this page is to be believed Cyberstorm MK3 uses a mix of interleaving and what PC manufacturers today call dual channel RAM, two 32 bit modules supplying a 64 bit bus. Initial access latency is going to be limited by technology of the time but burst reads should be ridiculously quick as each ram access supplies two longwords and the interleaved access supplies the other two making up the 4 longwords of each 68040/68060 RAM access. It'll be complex to sequence and shuffle the extra longwords around, but performance should be very good. This would be a practical implementation of what @eharmon was speculating about.

Bustest score for CSMk3 at 75Mhz (I don’t think they can clock much higher than this due to board limitations) gives 72MB/s for long word read.

Not much new to report here. Working at a 256KB cache board that incorporates the 060 adapter, hopefully I'll get that routed over christmas break. Just something to play with. Two findings of interest, though:

Turns out the early revision 060s like additional voltage. A lot. Previously 65mhz was the razor edge for stability but bringing VCC to 3.6v changed that to 83mhz. A bit of airflow across the heatsink is required at that speed as otherwise it becomes unstable once hitting ~60 degrees C die temp. Maximum supply voltage is specified as 4v so we're still fine there. As far as I'm concerned that frequency is ideal since wombats do well at 40mhz bus.

I've added the ability to customize the MEMC timings to the ROM and purchased some 40ns 64mb SIMMs to play with. Not easy to come by, and the modules I found I had to add a regulator as they were intended for 3.3v systems though the DRAM is 5v tolerant. I was able to tighten the memory timings considerably - to the minimums supported by MEMC - with a corresponding performance increase in performance in memory-bound tasks. What's more interesting is while I added the option to soft-disable the onboard RAM as I've got a mix of 70ns and 80ns, it will still operate with the onboard RAM (and no simms) at the tightened timings. At some point I'd like to work through the timing diagrams in the MEMC datasheet and figure out what "safe" parameters would be for 40/50ns RAM.

The custom memory timings / onboard RAM disable can be used if building the ROM in an 040 version also - there's a single config option that controls that.

zigzagjoe said:

Not much new to report here

Click to expand...

On the contrary, your voltage and ram timing tweaks are pretty impressive!

Getting the best results from an 060 on a wombat clearly require a lot of experimentation and refinement, throwing the cpu in and getting it to work is just the beginning.