Bunsen
Admin-Witchfinder-General
http://bitchin100.com/wiki/index.php?title=REX_Overview
Now, granted, the 68k does not use a multiplexed address/data bus, but - does this stir any ideas?REX is a low power 1MB flash card custom designed to work with the [Tandy] Model [100]. The challenge for REX is to be able to accomplish a "write" in a socket designed only for "reads".
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The REX Communication Method
REX uses a unique approach to bi-directional communication in a read-only socket, which is 100% reliant on the architecture of the 8085.
Reads are simple - the socket is designed for Read Only.
Writes are the challenge, with the signals available.
The 8085 uses a multiplexed address and data bus, and the ALE signal is used to discriminate address from data early in the CPU cycle. Normally address data is captured on the falling edge of ALE. We use this fact to send data to REX embedded in the lower address byte.
REX watches the address bus for READ operations (signaled by /CS to the option rom socket), and listens to the lower byte.
To send data to REX then, one must perform a READ to the optrom socket, where the desired data is actually the lower address field. REX is clocked from ALE, so it will respond to stimulus from the bus on the falling edge of ALE.
REX mostly ignores this data, and acts like a normal option rom, until it senses the key sequence has been sent. When a sequence of 6 reads from addresses with specific bytes in the lower address field are seen, REX transitions from the default power up state into the command state.
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REX intercepts the address/data bus AD0-AD7, and the system communicates with the CPLD using data sent on these lines.
Data is sent to REX on the falling edge of the ALE signal. During this time, the address/data bus AD0-AD7 contains the lower address information for that CPU cycle.
So, in order to send data to REX, the data is sent as the bottom 8 bits of the ADDRESS, not the DATA, during a read cycle from the option rom.
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