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Reproducing the Lisa 2 Card Stack: The 512K RAM Card

warmech

Well-known member
As part of my ongoing efforts to resurrect my Lisa 2, I've stepped back to work on a much broader goal: the reproduction of the Lisa's card stack in full. While the motherboard and I/O board have been reproduced, they are either no longer in production and impossible to find (in the case of the I/O board) or exist in extremely low quantity. As such, after speaking with someone working on a similar endeavor, I've decided to press forward and start hammering away at the RAM and CPU cards. My goal at the end of the day is to provide a complete set of design files that would allow anyone with a Lisa 2 chassis to assemble a brain for it.

Starting with the RAM card, I pulled everything off of one of mine and got it scanned. The scans need to be redone (I didn't take the levers at the top into account and, as such, the top of the board appears slightly warped in the scans), but the ones I do have are attached here. Once I have better ones, they'll go into a GitHub repository and get posted here. With scans of the front and back of the depopulated board and a set of the schematics in front of me, I got to work. After forty-ish hours and eleventy billion traces later, this is the result:

lisa_ram_card_traces.png

new_pcb_render_front.png

This is obviously a prototype, and I actually have a question for those out there that know hardware better than I do. The schematics make a distinction between DGND (attached to the ground leads on RAM and RAM bypass caps) and GND (attached to ground on everything else), but the DGND and GND paths are connected. I would have assumed that these would be kept separate, but they're not and I'm not sure why. Anyone able to enlighten me as to why that's the case? Also, the original is a four layer PCB; I've made this as a two layer for now (expanding it to four layer is trivial work, thankfully), but I'm wondering if it genuinely needs the additional two. If you look at the rear scan I attached, you can see that the two RAM sections and the middle logic section are separated on plane three; plane two is completely connected, however. What is the rationale behind this if the grounds are just connected anyway? I'd like to try to keep this a two-layer board if the weird ground planes can be ignored; the cost to manufacture is significantly higher for four layers.

This card still has a bit of work to do before I call it ready to have some produced. I'm having some folks put their eyes on it to make sure there aren't any glaring errors and will upload a set of design files shortly if anyone here wants to take a look as well. Hopefully I can get this thing entirely error free prior to ordering a set, as I really don't want to find myself ordering multiple batches of these, lol. Also, please excuse the component labels, they're just kind of slapped on there at the moment - this thing will look a bit nicer when it's done.
 

Attachments

  • lisa_ram_card_scans.zip
    5.8 MB · Views: 1

ScutBoy

Well-known member
This is great and needed work, so don't take this the wrong way, but if you want to be a hero to the Lisa community, come up with a replacement backplane board to replace all of the ones that were destroyed by battery failure.

I think the Sigma Seven guy made these, so maybe that's enough, but they also were not cheap.
 

stepleton

Well-known member
Nice work! Would you consider mentioning this project on http://lisalist2.com/ ? There are a fair few knowledgeable hardware folks who hang out there, including the "Sigma Seven guy" (aka James MacPhail).

Among the projects mentioned on lisalist2 lately is a recreation of the backplane board. See this thread and this GitHub repo. We can be our own heroes together.

Personally, a fun thing I'd like to see is a Lisa RAM board made as small as possible. It wouldn't look the same, but you could probably just have the barest stub of a PCB poking out of the motherboard slot. I think it would be a gas and occasionally think of working on that, but then I think of the million other projects I keep making for myself.
 

stepleton

Well-known member
Regarding the separate grounds: could be EMI compliance? Cf. this Twitter thread

I've noticed similar separated grounds on the Lisa AppleNet card I partially reverse-engineered. (Just about everyone reverse-engineers Lisa hardware! :)) Although this pair of grounds could serve a different need. The card has a digital ground and an analog ground, and they're connected via an inductor. You can see the arrangement at the bottom centre of this schematic.
 

warmech

Well-known member
Nice work! Would you consider mentioning this project on http://lisalist2.com/ ? There are a fair few knowledgeable hardware folks who hang out there, including the "Sigma Seven guy" (aka James MacPhail).

Among the projects mentioned on lisalist2 lately is a recreation of the backplane board. See this thread and this GitHub repo. We can be our own heroes together.

Personally, a fun thing I'd like to see is a Lisa RAM board made as small as possible. It wouldn't look the same, but you could probably just have the barest stub of a PCB poking out of the motherboard slot. I think it would be a gas and occasionally think of working on that, but then I think of the million other projects I keep making for myself.
I've been in contact with them about their work so far and I'm beyond impressed. I'm hoping we can collaborate on some Lisa stuff in the near future.
 

ScutBoy

Well-known member
Nice work! Would you consider mentioning this project on http://lisalist2.com/ ? There are a fair few knowledgeable hardware folks who hang out there, including the "Sigma Seven guy" (aka James MacPhail).

Thanks - I was blanking on the name, and on my phone so it was not convenient to go out and look up his name.

Apparently I've been lanquishing over keeping up with developments in the Lisa world. Time to get my Lisalist subscription figured out and back up and running....
 

compu_85

Active member
One suggestion: When you make your respin of the ram card, make it so you can do 2mb. Despite what the documentation says, I've had no issues with Lisa OS, Xenix, or UniPlus+ with just a single 2mb AST card installed.

-J
 

cheesestraws

Well-known member
Regarding the separate grounds: could be EMI compliance?

Yeah, EMI or noise affecting the operation of .... something .... would probably be my guess here. It is only a guess, though.

This is good stuff. I'd second what @compu_85 said; if you can make this do 2mb that would be a really useful thing.
 

warmech

Well-known member
Bit of an update.

The preliminary draft of the 512K card is done and ready for review. This is the two layer version; I'll be working on the four-layer soon, but wanted to put the two layer board to paper first. I want to sleep on it and look over it one more time in the morning before pushing to GitHub, but here's a little preview:

512K_card_preliminary.png
 

warmech

Well-known member
Like these?

FYI, I did reach out, and apparently neither are available. 😞 I was seriously considering buying the bare board... so if you spin an equivalent up, I'm in. 😀
Curses!

Actually... give me a few hours.

Edit: Oh yeah. It's all coming together. Won't be ready tonight, but I'll probably have an update tomorrow evening. Stay tuned, folks.
 
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warmech

Well-known member
I've got high res scans of that card if you want them:


If you wanted to go the DIP memory route, I was thinking more along the lines of the AST card. There are these plans for turning a 512k card into a 1mb card: https://lisaem.sunder.net/cgi-bin/bookview2.cgi?zoom=0?page=23?book=6?Go=Go

-J

Welp, that solves the problem I was retooling a new board around! I've been scouring for images of that board and just kinda gave up after a while. I knew I'd seen that rewiring diagram somewhere before, so I started a new PCB last night that just used the added/removed logic to connect to SIMM sockets. Now that I have these, though, I can do it the right way.

Thank you so much for providing these - this is invaluable information that's absolutely worth preserving! :D
 

warmech

Well-known member
Time for an update of sorts!

Using the scans provided by @compu_85, I've recreated the 2MB card in its entirety with the exception of two traces, and I wanted to solicit input as to how these might be dealt with. First, a couple of items for context:
  • As the board has no discrete traces for distribution of power or grounding (with the exception of the connections from the decoupler caps to the power inputs on the ICs), it is assumed that the two inner layers are GND and +5V.
  • If the above assumption is true, it is also assumed that the inner layers are uninterrupted by additional traces. I would argue that this is supported by the fact that, in the scans, no contrasting areas are present on the visible sections of layers beneath the top and bottom ones and the layers are uniform in "color" (the scans are greyscale) and contrast, with the exception of some minor banding that is an artifact of the scanning process.
So, here's where I'm at. There are three 74LS373s that handle address latching located directly above the edge connector. Pin 1 (output enable, active low) of each of those LS373s is tied together, but there does not appear to be any further connection.

Screen Shot 2022-08-01 at 3.25.41 PM.png

The back of the board is equally as puzzling:

Screen Shot 2022-08-01 at 3.27.52 PM.png

The equivalent chips on an Apple 512K card are tied to +5V via the DIP16 resistor pack at the top edge of the card, but that card's layering is structured differently than this one. While they're both four layer cards, the Apple one has two internal ground plane layers - one for the primary ground plane, and another that is partitioned into separate digital ground planes for the two RAM sections and the control logic in the center. As such, it has a direct trace leading from that resistor pack to the /OE pins on the two LS373s that perform latching operations (see below). Taking the earlier assumptions into account, the Sun card has no such need for discrete power and ground traces. The thing that I just cannot figure out is whether these three pins are wired directly to the power rail on this card or not. Does someone with a little more experience in 74-series logic maybe have some insight on what these could be doing?

Screen Shot 2022-08-01 at 3.32.51 PM.png

The other oddity is this little jumper in the middle of the board:

Screen Shot 2022-08-01 at 3.26.12 PM.png

All the photos I've seen of this card have that jumper unpopulated. What I cannot determine is where that via connected to the jumper goes - ground, or power? The bottom lead connects to the /SFER (soft memory error) pin on the edge connector, which the Apple schematics list as having no connection at pin 50 (and I checked my depopulated Apple card - it's NC there, too). According to the hardware docs, pulling /SFER low tells error correcting code to handle any correctable errors in memory, so my initial thought is that soft error checking must be disabled by default. However, the pin (active low output 4Q) that jumper connects to on G5 is still tied to that via; if my assumption that there are only two uninterrupted ground/power rails in the inner layers is true, then my guess is that that via is tied to a ground connection so as not to leave the pin floating. Just a guess, but the best I have at the moment. If anyone might be able to weigh on with their thoughts, my ears (eyes?) are open to any suggestions.

Also, a progress pic:

2m_prelim.png


Edit: the MEM1 jumper also looks weird to me, but it may just be because of how long I've been staring at this thing. I'm pretty sure it's just a set of NC pads that are used to store a spare jumper connector. The text of the manual states that MEM1 is already jumpered for the owner's convenience which, if you look at the pins leading into the jumper, makes sense as the trace at U2_12 diverts away from the jumpers altogether and hits the same NAND gate at G11 as the other three SIMM bank jumper connections.

Screen Shot 2022-08-01 at 4.33.31 PM.png
 
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lisa2

Well-known member
The jumper in the middle is for the RamBo 4 Meg Mod. It uses /SFER as an addtional address line.
 

warmech

Well-known member
The jumper in the middle is for the RamBo 4 Meg Mod. It uses /SFER as an addtional address line.
Are you kidding me, lol? That's amazing! I had no idea these cards natively supported the 4MB mod. Hmm... this explains the extra address lines beyond 8. Man, there's a lot on this board that suddenly makes much more sense now - thanks! I assume that pin is otherwise tied to ground through the via?
 

compu_85

Active member
Pin 1 of U5, U6, and U7 are tied to ground. The Via on the J jumper also goes to ground. (on my populated board anyway)
 
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