recapped LCII plays chimes of death, no startup chime

[bigmessowires]

I'm not sure where you're getting 1.06% from? I see a score of 19.1 versus 18.0, so that's about 6% faster. This squares with what I'd read somewhere else saying the 68030 is about 5% faster than the 68020 at the same clock speed, due to the additional cache it has.

On a different topic, I'm surprised to see the CPU performance difference between the SE and Plus in your results. They are both 8 MHz 68000 on a 16-bit bus, and I'd always thought their performance was identical. But I dimly remember something is different about how they interleave access to RAM between the CPU and the video circuit.

EDIT: Apparently I wrote something about that exact topic, 12 years ago: https://www.bigmessowires.com/2011/08/25/68000-interleaved-memory-controller-design/

 

[Phipli]

I'm not sure where you're getting 1.06% from? I see a score of 19.1 versus 18.0, so that's about 6% faster. This squares with what I'd read somewhere else saying the 68030 is about 5% faster than the 68020 at the same clock speed, due to the additional cache it has.

Yup. Just me being daft. I read it and forgot to multiply by 100 for 106% of the base number. Don't mind me. One of those days.

More in line with what I was expecting.

On a different topic, I'm surprised to see the CPU performance difference between the SE and Plus in your results. They are both 8 MHz 68000 on a 16-bit bus, and I'd always thought their performance was identical. But I dimly remember something is different about how they interleave access to RAM between the CPU and the video circuit.

So this is due to the improved SE design like you say, wrt the video.

The CPU gets 100% of the memory time during the vertical blanking with both machines, but on the Plus, it only gets... 50% I think it is... of the time during the screen draw period, while on the SE it gets 3/4 of the time???. The way they did it was set up the SE so that it had a bigger shift register and it read two 16bit words of the memory and cached it, instead of a single 16bit word on the Plus. It was able to read two words in not much more time than one, and so left more time for the CPU to do its thing before the video circuit needed memory again. The CPU can access RAM during screen drawing the whole time the shift register clocks out its data...

If I remember correctly, the 32bits the SE reads is half video data and half floppy drive spindle speed data... for reasons.

Edit : to be clear, I need to verify the timings, but you get the idea, the RAM is available to the CPU for periods which are twice as long during the screen draw phase.

 

[Phipli]

EDIT: Apparently I wrote something about that exact topic, 12 years ago: https://www.bigmessowires.com/2011/08/25/68000-interleaved-memory-controller-design/

Didn't see your edit