Trash80toHP_Mini
NIGHT STALKER
Fabulous read. Loved every bit of it until my skull imploded at 0x21FC.
Finally, not to put a damper on the efforts, but I feel this is going to be a long shot. I mean, wouldn't MicroMac have made an SE/30 adapter to increase sales of this product? They made them for the IIsi, IIx, and IIcx, so with the SE/30 mysteriously missing I can only surmise that there is some technical limitation we're going to bump into. Unless of course, the omission is due to the sealed up nature of the compacts, and MicroMac didn't want to support end users in that endeavor.
Discussed this clocking "suspicion" with Bolle already (We're quite busy behind the scenes ;-)).One more thought: The socket of the IIx and IIcx run at the same 16MHz clock as the SE/30's, but timings may be right on the edge for supporting such a slow bus as compared to the 25MHz bus of the IIci and 20MHz bus of the later IIsi. Wondering if buffering trows the equation just far enough off that the SE/30 was unsupportable. I have no clue as to possible efficacy of rework substitution of 74HCT buffering on one or both sides of the SE/30 PDS, whether it is in fact appreciably more responsive than 74F logic or if this makes absolutely no sense theoretically. @Bolle whatcha think?
I'll pipe down now. :mellow:
Figured he'd be in on this. []Discussed this clocking "suspicion" with Bolle already (We're quite busy behind the scenes ;-)).
Like a question, a WAG is not stupid by definition. A WAG can be silly, misinformed, way out in left field or outlandishly out side the box For a question, the stupid one goes unasked as WAG not floated. I think there's something about incandescent light bulb development loosely related to that. []I traced the CPUclk (SE/30: 15.6672MHz) coming from the PDS slot to both FPGAs 'TclkIn' pins. Also, the 040s 33.3Mhz clock is fed in there. So my initial (stupid) WAG was, that these two clock-domains used in the FPGA VHDL/Verilog might get into some troubles (Given the FPGAs have to do the dynamic bus-sizing translation between 030 and 040). This would lead to different clocking-ratios:
- Mac IIci ~x1,25
- Mac IIsi x1.6
- SE/30 ~x2.10
Makes sense, that oomph is there to drive an expansion bus spec limited to just two TTL inputs while the IIci Cache Slot was designed to support just one. The IIsi PDS would be the same spec, but for the clock ratio disparity.Who knows how clever their state-machines were designed.... but then it stroke me: Dang! The II[c]x has the very same clocking and these were supported by direct-to-socket adapters.
And if my eyes aren't betraying me, the clk-pin on @nickpunts adapter is going straight to A38 on the PDS slot. That said, Nick, it would be interesting to know where A3 (/BUSCLK) is connected to on your adapter...
Next up was the load being put on the clock-signal. I have the short version of @Bolles adapter, sitting on the NIC which also lives off the clock-signal, but "Designing Cards and Drivers..." has the answer:
This means litte SE/30 has more ooomp to the CLK signal than his bigger cousin.
- SE/30 - Drive: 40 uA /0.4 mA, 30 pF
- IIci - Drive: 10 uA/0,1mA, 15 pF
In WAG mode, methinks the quality of your schmoozing time would increase dramatically by building an interposer. But on built for the 030 socket interface and gated for three states: straight thru, 74F573 type and 74HC(T)573 type buffered latches or the equivalent of whatever buffer IC is used to drive the PDS of the SE/30. That would be the bottleneck for SE/30 adaptation the way I see it in this table:So my current "hot trace of the week(tm)" is timing - i.e comparing different runs with my logic analyzer etc. - also I think I won't get around building a 1:1 PDS-interposer to eavesdrop my IIci while smoozing with the Carrera.
LOL - love you too, bro!While digging through the init geekdot kept insisting that we had a hardware timing issue which resulted in the crashes right when the init loads to enable the C040.
I wouldn't believe him at first but he wouldn't stop :-*
...and QuickDraw just uses, whatever method the driver offers to set pixels. So what the heck, I've disassembled the SE/30 driver-ROM, too.Right now we are not sure where the onboard video issues originate. QuickDraw was a suspect but we did not totally rule out that it still might be a timing issue of some sort after all.
I tried delaying the clock using a 74LS31...Trying to find out if fine-tuning the phase of the 16MHz clock gets us somewhere is the next thing on the list.