Another IIci ROM hack

[tt]

Here are my pics, sorry for the poor quality. I can take better ones later if needed.

The top ROM is from a IIfx and bottom ROM is from a IIsi:

Backs:

Fronts:

Wow, your CAD looks pretty close to complete! It looks like they use vias to get pads connected to the front and back when I look at the images more closely.

X-ray is not necessary, but I might have some extra machine time to use since the lab I work with charges a 1hr minimum. If the board designs are identical, then an image match is a good way to check to make sure everything is in the right place.

 

[dougg3]

Oh wow! Thanks for the scans! Those are very, very helpful! Glad to see Apple did a similar thing by using the bottom layer to connect the pins near the top of the PLCCs on the IIsi one, so I'm not totally crazy

Ah that's true. I didn't realize it was convenient enough for you to do the X-rays. Cool!

Yeah, I noticed a similar thing with the vias on that LaserWriter ROM SIMM I got. Doesn't seem like it would be too bad to use a bunch of vias to stick the other side in place. Not sure how I'll connect some of those VCC pins together though...looks like Apple just left some of them not connected, so that would probably work.

 

[Trash80toHP_Mini]

. . . so I'm not totally crazy

HEH! That'd be my job description! )

Don't bother putting pads on the backside of the board. As I understand it, the SIMM spec isn't as thick as the standard FRP blanks used by the fab houses. If there's no metal on the backside of the pad area, we can run them over a router bit as I described above, instead of filing away at them the way gamba had to do in order to get the gamba/trag SIMMs to fit.

You might want to move the plated thru holes to the backside far enough away from the front side pads to give a better margin of error for setting up a Router Table/Sliding Table combo.

What's the maximum possible size for an expanded area ROM SIMM for the IIci, SE/30 and IIsi? :?:

If anyone has all three machines, a cardboard mock-up that'll clear all obstacles when installed in those three machines would be a good starting point for an in-place programmable EEPROM setup.

 

[tt]

I guess X-ray wouldn't help too much in this case since the IIsi ROM is also 512k, so it will be different for a 1Mb ROM according to Trag due to the different pin-out.

I think having pads on the front and back might be useful for redundancy/reliability in the socket. It would be a pain to diagnose if your machine doesn't boot one day just because of a marginal contact. It looks like dougg3 is designing it for fab at a board house. If the board fab says they can make the proper thickness, then why not just go for the whole package?

Overall it looks like the placement of components is good. Looks like the caps are moved over for clearance for sockets in case you want to use them? I can't comment on the actual connections. dougg3, did you have a schematic associated with the board or is it based on physical placement alone?

 

[dougg3]

. . . so I'm not totally crazy

HEH! That'd be my job description! )

Haha, I think it fits me pretty well too!

Don't bother putting pads on the backside of the board. As I understand it, the SIMM spec isn't as thick as the standard FRP blanks used by the fab houses. If there's no metal on the backside of the pad area, we can run them over a router bit as I described above, instead of filing away at them the way gamba had to do in order to get the gamba/trag SIMMs to fit.

I agree, but bigmessowires pointed out a very reasonably-priced PCB place that *does* do the correct board thickness. So I may be able to get away with not having to worry about the thickness at all

You might want to move the plated thru holes to the backside far enough away from the front side pads to give a better margin of error for setting up a Router Table/Sliding Table combo.

Are you talking about the vias that are near the SIMM connectors? I should be able to do that pretty easily if we do end up having to use the router.

What's the maximum possible size for an expanded area ROM SIMM for the IIci, SE/30 and IIsi? :?:

If all the lines are hooked up in the pinout that's shown in the wiki, there are 21 address lines that are actually used, for a total of 2^21 = 2*1024*1024 addresses, and each address actually points to four bytes, so that would be 4*2*1024*1024 bytes or 8 megabytes. Is my math right? The SIMM design I'm making hooks up all 19 of the standard PLCC32 address lines, which would allow for a maximum of 2 megabytes of ROM space if we used 4 megabit flash chips.

If anyone has all three machines, a cardboard mock-up that'll clear all obstacles when installed in those three machines would be a good starting point for an in-place programmable EEPROM setup.

True, true! I didn't think about needing it to fit in the SE/30 and IIsi and whatever else there might be!

I guess X-ray wouldn't help too much in this case since the IIsi ROM is also 512k, so it will be different for a 1Mb ROM according to Trag due to the different pin-out.

If the IIsi's ROM is 512 kilobytes in size, that means that it uses four 1 Megabit ROMs for a total of 4 megabits, or 512 kilobytes. Trag was saying that 1 megabit and bigger ROM chips use a different pinout from the 512 kilobit and smaller chips. Since the IIsi does use 1 megabit chips, the IIsi's SIMM should be spot on for the correct pinout Except it probably won't have some of the higher address lines connected -- I'll check on that, but it shouldn't be too bad to add.

I think having pads on the front and back might be useful for redundancy/reliability in the socket. If the board fab says they can make the proper thickness, then why not just go for the whole package?

As long as Seeed Studio works out, I definitely agree

Overall it looks like the placement of components is good. Looks like the caps are moved over for clearance for sockets in case you want to use them? I can't comment on the actual connections. dougg3, did you have a schematic associated with the board or is it based on physical placement alone?

Thanks! Yeah, that's why I moved the caps, to make room for the sockets. I'm definitely not against moving them elsewhere -- even to the back of the board if the need arises. I think they're supposed to be as close to the chip's pins as possible... No, I didn't use a schematic because FreePCB only does the board layout part of things. I'm probably crazy for not starting from a schematic...

 

[Trash80toHP_Mini]

I was actually asking about the physical size of an expanded PCB area. A higher and wider than normal ROM SIMM could enable addition of the extra gobble-de-gook necessary for doing a SIMM that's programmable while inside the box.

The overall shape of the PCB would have to be a bit funky to make it wider, but what about this hack isn't? )

 

[tt]

Since the IIsi does use 1 megabit chips, the IIsi's SIMM should be spot on for the correct pinout

Oh yeah, thanks for clarifying, I am getting bits and bytes confused. I'll x-ray the board in any case if I can. If it doesn't help, it will at least be a cool image for the collection. I might also x-ray a IIcx DayStar socket board as well, but that's another topic.

As long as Seeed Studio works out, I definitely agree

Yeah, it is a sweet deal. With prices that low, I would even spring for a sporty red color. }

I'm probably crazy for not starting from a schematic...

I would do it that way if there is no schematic avail, but I am crazy.

 

[bigmessowires]

I'd forgotten about all the little notches you'll need on the SIMM, which you can see in tt's photo. You'll need to include those in the board outline, unless you plan to use a router tool to cut them yourself afterwards. One problem is that I'm pretty sure Seeed only does rectangular boards for the price they offer-- that's part of why it's so cheap. I think Batch PCB and Dorkbot PDX will do arbitrary board outlines, but I'm not sure if they offer the 1.2mm thickness you need. You may have to hunt a little to find a place that will do arbitrary outlines *and* 1.2mm thickness for a reasonable cost for a hobbyist, but I'm sure it's doable.

Your layout looks pretty good to me. I wouldn't sweat the capacitor placement too much-- closer to the power pins is better, but it'll probably still work fine even if they're further out.

If you do get the 1.2mm thick board, then I'd suggest putting contact pads on both sides, like you planned.

I don't think you should need a 4-layer board. If you have trouble fitting all the traces, try the method of routing everything on the top side horizontally and bottom side vertically, with no diagonal traces.

 

[trag]

One problem is that I'm pretty sure Seeed only does rectangular boards for the price they offer-- that's part of why it's so cheap.

Their description implies that they accommodate slots:

Minimum slot 1mm*1mm

In other words, larger slots are okay, but no really long slots are allowed. The little notches needed by a SIMM should be fine.

Your layout looks pretty good to me. I wouldn't sweat the capacitor placement too much-- closer to the power pins is better, but it'll probably still work fine even if they're further out.

Use really thick traces for the capacitors. One thing you can do is put something like a 39 mil via on end of the Vdd and Vcc pins and put the capacitors on the back of the board, right next to the vias.

If you do get the 1.2mm thick board, then I'd suggest putting contact pads on both sides, like you planned.
I don't think you should need a 4-layer board. If you have trouble fitting all the traces, try the method of routing everything on the top side horizontally and bottom side vertically, with no diagonal traces.

I agree. Two layers should work fine. My Mac IIfx SIMMs are two layers and they work.

If you look at this image, between the first and second chips from the left, you'll see a bypass cap connected with relatively long thick traces. Also, note the copper fill around the edges of the board.

In the following picture, you can see the bypass cap for the other memory chip near the center of the board. Again, note the fill around the edges and sometimes near the middle of the board. I filled Vcc on the front of the SIMMs and Vdd on the back.

Same thing, but different model, and slightly cleaner layout, because there was more repetition:

 

[dougg3]

Yeah, my board outline is in the screenshots, it's just dark blue so it's hard to see. I also noticed that on Seeed Studio's forums someone asked about making a circular board or a board with rounded edges and those both seemed fine. So I think they will be able to do it I'll definitely put contacts on both sides now.

Good idea about putting the capacitors on the back of the board with the thick traces between the ground and VCC pins. I'll go for it.

I noticed on tt's picture of the IIsi ROM SIMM, the VCC trace out of the SIMM contacts is really thin. I was planning on making the VCC traces a lot thicker as you can see from my design. Probably doesn't matter but I'd rather be safe than sorry!

Looks indeed like 2 layer will be fine. I was just nervous because my original design was more complicated than it needed to be. I like the idea of ground fills on one side and VCC fills on the other. Doesn't that basically make the board a big capacitor, too? Anyway, I'll see what I can do!

Nice pics, trag! Those are awesome 64 pin IIfx SIMMs. Thanks for showing your designs!

My coworker also suggested moving the vias that are really close to the PLCC pads (like on the ground pins on my screenshot) away a bit so if we do the reflow stuff, the solder won't flow into the via. He also said he thinks he could probably hand solder one of those surface mount PLCC sockets but it would be tough. We'll see...

 

[bigmessowires]

It can definitely be hand-soldered. I've hand-soldered SMT PLCC chips, as well as QFP chips with even smaller pin spacing (down to 0.5mm spacing). I used the "drag solder" technique with a standard soldering iron. Google for video demos if you're not familiar with the technique. A toaster over reflow would probably work too, but I've never done that myself.

 

[dougg3]

Oh I know it can be done when the chips are out in the open (I've done it too with a 0.5 mm LQFP), but I mean he says he can get the pins soldered despite the plastic socket material being in the way, like from that picture I posted the other day. I don't think the drag method would work since those little plastic doodads are there between some of the pins. I figured the plastic being in the way would be a showstopper, but he thinks he can squeeze in there and still solder it. Either way it will be a pain for assembly, though.

The oven reflow works pretty well, especially if you have a solder paste stencil so you can just squeegee solder paste on, stick on the parts, and bake it.

 

[tt]

Here's the x-ray of a IIsi ROM:

 

[dougg3]

Haha, that is awesome! Not only is it very useful, but it is really cool to see! Thanks for x-raying it!

I really like how you can see inside the PLCC chips.

 

[trag]

It's probably too late to help, but here is the front layer of my SE/30 ROM layout. It may be incomplete, such as missing connections or details remaining to be fixed. Apparently the last time I worked on this was September of 2006.

And the back layer:

The file with the design in it is in this folder:

http://www.prismnet.com/~trag/Classic%20Mac

I used Osmond PCB for the design, which is excellent Mac based PCB layout software:

http://www.osmondpcb.com/index.html

When I started using it, it was in Beta and free. After it went commercial, I bought a copy for $200 and consider it well worth it. Apparently it is $79 now.

You can download Osmond and use it to open my design. Without purchasing license you won't be able to print it, I think. If it's under 700 pins then it will be printable/exportable.

 

[Trash80toHP_Mini]

Since we're also on the subject of IIfx SIMMS all of a sudden . . . [] ]'>

I always wanted to look into hijacking the parity lines by cutting them at the memory controller and patching them to any available/unused bank/row select pins to increase the capacity of a custom SIMM design to make use of the extra signals which would suddenly become available at the SIMM Slot level and as quiet as a church mouse running through the parity traces.

IIrc the fx has something like a 1G memory space . . .

. . . whatcha think trag? }

 

[dougg3]

No idea on jt's question...I'll leave that for trag and the other hardware experts

I have been looking at the Apple SIMMs and the X-ray image. I was completely wrong about VCC's traces being thin. They are nice and thick -- and it appears the IIsi ROM SIMM has more than 2 layers. If I'm not mistaken, there is a VCC plane in the middle of the board, and maybe a ground plane in the middle of the board too. Can anyone confirm that? Here are my reasons:

• I don't see any connections between the VCC pins on each chip (3rd from the right on the top when looking at the image of the top) to any other chips, but each one of them has a via (3 of them are hidden under the chips) that seemingly goes to nothing -- it's not connected to anything on the bottom layer. That kind of hints that there's another plane running underneath the board.
  
• All of the VCC pads on the SIMM connector don't go to anything on the top or bottom layer.
  
• The ground pins on the first and third chips from the left have vias that also seemingly go nowhere. So they must be going to some kind of a ground plane underneath...

So it may be better to stick with something closer to my original design and/or trag's design that he just shared.

 

[Trash80toHP_Mini]

By George, I think you've got it! :approve:

Take a look at the bottom right corner of the X-Ray. It clearly shows three different planes by the beginnings and ends of their shading overlaps.

 

[dougg3]

Ah, that's right! You can see a similar thing on the left side of the board too. I still can't get over how cool that X-ray image is

 

[tt]

Yes, I was wondering about the number of layers last night while I was playing around with trace routings, some things were not quite making sense if the board was just 2 layers.

Thanks Trag for posting your design! Maybe we should all collectively vet one design and generate gerber files after its confirmed to appear correct.

Is there a schematic for the ROM somewhere?