ProtoCache1 - IIsi/SE/30 PowerCache Adapter Prototype Development

[Trash80toHP_Mini]

Just wondering if my PLCC20 to DIP20 adapter might make sourcing compatible parts any easier. Looks like it plugs into your existing socket and is good to go with the more modern IC Package installed. Might proper PLCC parts be more readily available?

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[trag]

Joe, are you good on PALs and GALs?   I have a supply in the attic.  I can check my inventory.  I know I have some 16V8, but I can't remember what package(s) they're in (PLCC vs. DIP).  I might have both.

 

[joethezombie]

Thanks for the offer trag!  I just bought a bunch off eBay a couple weeks ago so I'm set for now.   I just need to get back home and tinker with the logic.  I think we are nearly there with it.  I also have some of the good PLD experts from jammarcade.net helping me out with some ideas that could help this last hurdle.

 

[Trash80toHP_Mini]

Have you looked at the overall operation of the adaptation in terms of which changes are doing what to the signal connections? Working out a truth table of known changes to logical operations of the PDS/IIci bus could be very useful. Extrapolating from there might help in figuring out what must be going on in the GAL from the operations they must be completing.

An analogy might be that you're stuck looking at the branches of the GAL tree and missing the forest of logical operations of the SE/30 and PowerCache which might indicate the necessary arrangement of the leaves on your branches?

Dunno, this is one long Peanut moment for me.

[/Jeff Dunham/Peanut]

 

[Trash80toHP_Mini]

In another thread omidomo brought up an interesting point.

When I got my cards, I was getting the simasimac screen followed by the unhappy boot crash sound. Sakai-san informed me that the simasimac was normal as I had maxed out RAM, and the DayStar does it's own thing with the ROM. I was still not getting past the breaking sound with both cards, which lead me to purchasing the Hyper power supply from Artmix who had a few for sale at the time.

If Artmix was selling a turbocharged version of the SE/30 PSU, it's likely because their PowerCache/adapter/passthru card combo was taxing the rated power limits of the PDS. Might it be advisable to design provisions for PDS power cutout and a connector for an aux power supply or outright ATX conversions into our adapters where applicable? I'll have to hit the docs to find out what the power rating of the PDS would be.

ISTR some graphics cards requiring external power.

If we're making provisions for using all available interrupts and the PowerCache on the PDS, such seems advisable to me.

 

[omidimo]

Pulled from the Archive:

• Accelerator, enhanced power supply unit for driving large capacity HDD.
• Although it was designed as a product version, due to various circumstances, it was decided to distribute it as a prototype final version. By example, for small volume production, reservation is necessary. (Please contact us for delivery date.)
• With the ultra-large capacity of 145 W (MAIN) + 45 W (SWEEP) newly developed, it is possible to move 2 GB or more of the latest hard disk, 16 M SIMM, Turbo 040, etc. with leeway. (It is a special model which doubled the SWEEP of the conventional reinforced power supply, about twice the power of genuine power)
• With no fan design, it achieves the same quietness and ultra low noise as the normal power supply. Moreover, by using the newly designed flyback transformer of HC specification, it becomes possible to obtain images with excellent visibility.
• Avoid accelarator errors with phenomenal ripple characteristics.

 

[Trash80toHP_Mini]

Sounds  to me like it's time to develop a prototype ATX conversion designed to fit within a stock PSU case.

It should re-purpose the original AC connectors/switch etc. as I'm doing with the SuperIIsi PSU. No cables involved there, but the sweep cable would be desoldered/redeployed as I'm using the and pass a pair of Multiconnector power cables straight through the grommet. The 300W FlexATX  PSU in my BG3 hack has a cable with one FDD and two MOLEX connectors.

Dunno what voltages are on the four pin ATX mobo connector extension offhand, but if one is 5V, that female or a PCB connector for FDD or SATA(?) ought to be easily sourced for the PowerCache Adapter.

 

[joethezombie]

Sounds to me like it's time to develop a prototype ATX conversion designed to fit within a stock PSU case.

i did this with a flexatx power supply here:https://68kmla.org/forums/index.php?/topic/229-beefier-power-supply-for-se30/?p=315680

interestingly enough, one of my se/30s came with a 3rd party power supply that was made for accelerators and video cards. i’m on mobile and can’t find my thread about it, but it was made in salt lake city.

Edit: found it:

https://68kmla.org/forums/index.php?/topic/29112-strange-power-supply-in-se30/?hl=party+power+supply

 

[joethezombie]

Back to the PAL

Have you looked at the overall operation of the adaptation in terms of which changes are doing what to the signal connections?

Yes, I think everything is correct other than the cache enable. I theorize that the PAL is looking at the address range to determine if it is in the cache memory space, and asserting cenable based on that and some of the other states. I have a spiffy new 16 channel logic analyzer waiting for me at home, so I can get a better idea of what's happening when I get back.
My bet is if we were to drop the cache portion of the PAL, it would work fine for accelerators that have cache onboard, but cache-only cards wouldn't function. The artmix board for example doesn't look at the address space.

 

[Trash80toHP_Mini]

Cool, figured you had, but just thought I'd ask if that didn't happen to be the case. [] ]'>

Could the PAL be checking to see if the video subsystem is using memory mapped to Slot $E? My analysis of which Macs had which slots implemented/available against which had active or passive PowerCache adapters would indicate that your conflict would be polled in memory mapped to locations dedicated to the Video subsystems of the IIsi/SE30 which are implemented in PseudoSlot $E. Wherever $E is implemented, the adapters are active. Wherever $E is unimplemented, the adapters are passive with no known exceptions.

Differences between your IIsi form factor specific adapter and the Artmix/DiiMO SE/30 adapters might be evident. I know you and others have tested IIsi adapters in the SE/30, but has anyone tested an SE/30 form factor specific adapter in the IIsi? If that subset of the adaptation doesn't work in the IIsi, you may have found something very interesting/relevant to the current problem.

 

[omidimo]

 

[Trash80toHP_Mini]

Is that an AT PSU with an adapter PCB to the left of the heat sink or all on one original board? ATX?

Converting an ATX PSU to power on and off with the stock switch as the old AT spec. PSUs did would seem to me to be the way to go for Macs not afflicted with soft power complications.

 

[omidimo]

I took the picture last year, so its all a bit fuzzy until I take the SE/30 apart again. You can make out the main board is a MEAN WELL product. The next time I am inside which is soon I will take better shots.

 

[Trash80toHP_Mini]

AT/ATX spec. will be interesting, the model number should tell that story. When did you buy it, way back when or fairly currently?

I'm beginning to think in terms of mounting the FlexATX PSU within its own skin inside the SE/SE/30 can and ducting/modifying airflow in and out of the stock PSU enclosure via existing perforations. PSUs are carefully designed for proper cooling and heat sinks are sometimes bolted up to/thermocoupled to the sheet metal enclosures.

The SE/SE/30 can's perforations would reduce the sound of the light duty/low speed setting fan by acting as a baffles in a muffler.

 

[omidimo]

I got it last summer, wait time was roughly two months as he made these on demand.

 

[joethezombie]

Could the PAL be checking to see if the video subsystem is using memory mapped to Slot $E? My analysis of which Macs had which slots implemented/available against which had active or passive PowerCache adapters would indicate that your conflict would be polled in memory mapped to locations dedicated to the Video subsystems [...]

Hmm.  jt, that's an excellent observation!  If we look at the PAL input pins 7,8, and 9; we see they are connected to address lines A0, A1, and A4 respectively.  I thought it odd that only those address lines are analyzed.  Why not A2 and A3?   Well you just answered that question for me!  If we have a look at the block diagram for the IIsi computer, we see those address lines A0, A1, and A4 are tied directly to the RBV (RGB Built-In Video).

 

[Trash80toHP_Mini]

I'm glad I was still able to help out.  [] ]'>  You guys are operating waaaaay above my head on the GAL project. :mellow:

This makes perfect sense to me, it's been my theory all along that the reason for active adaptation for the IIsi and SE/30 was that Cache Operations conflicted with their Video Subsystems implemented in PseudoSlot $E. Same kind of thing is true of systems such as the II and IIx where Slot $E is implemented in hardware along with Slots $9-$D. Whereas the IIcx had Slots $C-$E excised form its spec. Only passive adaptation was necessary because nothing could address memory mapped to Slot $E.

Looks like SE/30 video has A0-A7 tied to its internal video. What block of memory would be affected/defined by address A0, A1 and A4?

Because you're successfully running this IIsi adapter in the SE/30, polling those three lines must be sufficient to prevent memory conflicts in the SE/30 as well.

 

[joethezombie]

Note:

Concerning the mystery signal on pin A1 (reserved) on the PDS30 in the IIsi, which is connected to the PAL pin5.  From DCaDftMF:

Pin A1 on the IIsi expansion connector is /RBV -  An active-low chip-select signal for the RAM-based video IC. This signal can be used, along with further decoding, to enable signals for a cache circuit.

/CacheEnable(low) = /RBV • /RW • /A0 • /A1 • /A4 • /D0

/CacheEnable(high) = /RBV • /RW • /A0 • /A1 • /A4 • /D0 + RESET

/CacheFlush (low) = /RBV • /RW • /A0 • /A1 • /A4 • /D3

/CacheFlush (high) = /RBV • /RW • /A0 • /A1 • /A4 • D3

where • is Logical AND, + is Logical OR, and D0 is the logical complement of /D0
 

All other combinations of inputs should not affect the /CacheEnable or /CacheFlush outputs. The /CacheEnable signal should be set low when writing a 0 to bit 0 of the RBV register 0, and should be set high when writing a 1 to bit 0 of RBV register 0, or when the RESET signal is asserted. The /CacheFlush signal should be set low when writing a 0 to bit 3 of the RBV register 0, and should be set high when writing a 1 to bit 3 of RBV register 0, or when the RESET signal is asserted.
I think I just cracked the B5.oe equation.

 

 

[joethezombie]

Whoops, typo in the /CacheEnable(high) equation.  Should be D0, not /D0:

/CacheEnable(high) = /RBV • /RW • /A0 • /A1 • /A4 • D0 + RESET

 

[Trash80toHP_Mini]

Sweetness! :approve:

ISTR finding an undocumented "reserved or unused" pin on the SE/30 PDS in the SE/30 engineering schematic that was documented in the BOMARC schematic. I wonder if it's the same kind of thing or even the same thing? I'll troll my earlier threads to see if I can find it.