Do you have a link to the actual 68K emulator source code?
The 68K emulator is at 0x68000000 (1.5 GiB + 128 MiB) but I don't think it matters for Mac OS X.
Also, I know PCI has a tree structure, but do PCI cards just take up the IO space they need then? (given that RAM can reach 3.5GB on 32-bit Windows on a PCI PC).
PCI devices have BARs (base address registers) that indicate the address and size of the memory region. The size determines the possible addresses. A 1 GiB BAR needs to be on a 1 GiB boundary. That leaves only 4 possible addresses it can use in a 32-bit system: 0x00000000, 0x40000000, 0x80000000, 0xC0000000. That's why BARs are usually 512 MiB or less. The first PCI Macs have firmware that has BARs limited to 128 MiB. Mac OS adds a nvramrc patch to support 256 MiB. Later Power PC Macs support 512 MiB max. I created a patch for earlier Macs to support 512 MiB. I suppose a patch to support 1 GiB might be possible but probably only one of those could be supported using address 0x80000000 unless 0x4000000 is usable? 0x00000000 would cover exception vectors and RAM and 0xC0000000 would cover macio and ROM.
The tree structure of PCI refers to when you have PCI-PCI bridges.
First of all there are PCI Host bridges which connect to the CPU/memory bus on the host side and PCI devices on the downstream side. The PCI Host Bridge might have limits to its supported address range. In DingusPPC, the PCI Hosts are Bandit/Chaos/AspenPci and MPC106/Grackle.
Any BAR of a PCI device connected to a PCI Host bridge can have an address anywhere the BAR and the PCI Host bridge supports.
Next you have PCI-PCI bridges which can connect multiple downstream PCI devices to a single slot of an upstream PCI Host bridge or an upstream PCI-PCI bridge. The address ranges supported by a PCI-PCI bridge are stored in the I/O, Memory, and Prefetchable memory behind bridge address range registers. Downstream memory ranges have to fit in the upstream memory ranges. For this discussion, you can ignore I/O memory ranges since those don't use CPU memory addressing.
You can use
sudo lspci -nnvvv (from my pciutils fork for Mac OS X) to get a list of all devices and the starting address of BARs and the address ranges of bridges.
To get the size of BARs, you can use my lspci for Open Firmware script which gathers the info which can be parsed by a shell script that uses lspci.
For example, a Radeon 7000 has these BARs reported by lspci:
Code:
Region 0: Memory at 88000000 (32-bit, prefetchable) [disabled]
Region 1: I/O ports at 0400 [disabled]
Region 2: Memory at 80a00000 (32-bit, non-prefetchable) [disabled]
Expansion ROM at 80a20000 [disabled]
My lspci for Open Firmware script will add this info for each BAR:
Code:
00006810:88000008.f8000008 Region 0: Memory at 88000000 (32-bit, prefetchable) [size=128M]
00006814:00000401.ffffff01 Region 1: I/O ports at 0400 [size=256]
00006818:80a00000.ffff0000 Region 2: Memory at 80a00000 (32-bit, non-prefetchable) [size=64K]
00006830:80a20000.fffe0001 Expansion ROM at 80a20000 [disabled] [size=128K]
A PCI-PCI bridge will have these regions:
Code:
00:0e.0 PCI bridge [0604]: Actiontec Electronics Inc Mini-PCI bridge [1668:0100] (rev 11) (prog-if 00 [Normal decode])
Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
I/O behind bridge: 1000-1fff [size=4K] [16-bit]
Memory behind bridge: 80800000-808fffff [size=1M] [32-bit]
Prefetchable memory behind bridge: 80800000-807fffff [disabled] [32-bit]
A PCI device connected to that bridge must have it's BARs inside that bridge's behind ranges:
Code:
01:00.0 USB controller [0c03]: NEC Corporation OHCI USB Controller [1033:0035] (rev 41) (prog-if 10 [OHCI])
Region 0: Memory at 80803000 (32-bit, non-prefetchable) [disabled]
00010010:80803000.fffff000 Region 0: Memory at 80803000 (32-bit, non-prefetchable) [size=4K]
The
[disabled] qualifier comes from the memory and I/O enable bits of the control register.
