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Kai Robinson

Reverse Engineering the Macintosh SE PCB & Custom Chips for 1:1 reproduction

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On the subject of the axial capacitors, Personally I would just leave the board as is, If needed the axials can be substituted for normal radial lead ones without much trouble. This is what I ended up doing on all my Mac II series machines due to the difficulty of getting the axials

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10 hours ago, max1zzz said:

Personally I would just leave the board as is, If needed the axials can be substituted for normal radial lead ones without much trouble.

+1, I would also agree.  I'm guessing probably the main reason for doing otherwise would be as part of the first stage of Tindie sales to recoup the costs.  But otherwise, for the publicly available designs, definitely I would prefer 1:1 so that we can emulate the good old feeling of retrofitting unoriginal capacitors.

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8 hours ago, quorten said:

+1, I would also agree.  I'm guessing probably the main reason for doing otherwise would be as part of the first stage of Tindie sales to recoup the costs.  But otherwise, for the publicly available designs, definitely I would prefer 1:1 so that we can emulate the good old feeling of retrofitting unoriginal capacitors.

Actually the reason is actually because the axials are getting hard to find, and twice as expensive as the radials.

Like i said, ultimately, i'm doing this project to do something for the community as a whole.

 

Obviously it'd be nice to put these boards on tindie and recoup the costs of development, but even if i don't - ehh, i've still learned new skills and tried to help. 

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Looking at the fuzzy Macintosh SE schematic right now, a first try at a grayscale conversion and gamma-adjusted image rescaling seems to make at least some parts easier to read, albeit at reduced resolution.  I'm looking to try my hand at redrawing this if I think I can see sufficient detail from the originals.

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One thing you can do, is take the sprint layout of each layer, and import that into KiCad - then work backwards to a schematic. If you'd like me to take a screenie of each individual layer in sprint, you're welcome to them. 

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Ok - i've done a final revision of the silkscreen, and added the original 1977 Apple logo as the original Mac SE board used (despite the fact that by then, Apple used the Apple Garamond font...which was...wierd.)

I've also changed the size of the via's to 0.8mm with an internal diameter of 0.4mm, and tented them by excluding them from the solder mask - should look much more professional compared to the prototypes. 

macseboard-final-rev12a.JPG

macseboard-final-rev12a-rear.JPG

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So I decided to split up modernizing the Macintosh SE main logic board schematics into two stages.  The first stage is for my own proof that I can actually read anything meaningful off of the original scans: trace over vector graphics and typed text on the original schematic image.  It's almost finished, but not quite, it has a few text transcription errors (due to the difficulty of reading), but this is what I have so far.  Fortunately, there is a certain degree of redundancy in the text labels, and seeing the big picture clearly really helps too.

 

As it turns out, the reverse engineering on the PCB layout will indeed be helpful in correcting minor errors.  Like, resistor identifiers and values, having zero ambiguity on that.  Also, other things can easily be solved by consulting other tech specs like datasheets, the PDS slot documentation, and so on.

retrace_se_mlb_schem.pdf

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On 8/2/2020 at 6:36 PM, Kai Robinson said:

Also, you'll have to make the second schematic page from scratch, seeing as there seems to be none on the internet.

Judging from the 1/3 in the bottom right corner and the tiny text above it that appears to say "SHT" (sheet) in scans of other pages, I'd assume page 3 of the main logic board schematic is also missing, unless you've turned up something for that.  At least we have some hints about which components go on which pages based off of the numbers in parenthesis on the arrows to connections on other pages.

 

I'm feeling pretty confident now about my retrace of page 1, I'll be able to move to drawing up full MLB schematics in KiCad soon.  I still need to check the PDS pinout with a second source since I had trouble finding it.  Could someone provide a link?  My work is up here on GitHub.

 

https://github.com/quorten/macsehw

 

Link straight to the redrawn PDF.

 

The BBU pinout is definitely helpful!  Where did you get it?  It uses a slightly different terminology than the original deciphered schematic.  Also there are a few technical differences that I've spotted.  Possibly some of these might be a (deliberately) introduced error on the original schematic?

  • RDO0, RDO1, RDO2, ... (instead of RD0, RD1, ...)
  • 11 *ENTD1K mystery symbol (indicate inverted signal, replace EXTPDS placeholder)
  • 12 *EN245 (indicate inverted signal)
  • 13 ROW2 (RAM configuration pin, instead of generic VCC, though maybe it's really the same thing)
  • 17 MBRAM (RAM configuration pin, instead of *EOP for 53C80 SCSI controller)
  • 32 *IRQ (indicate inverted signal)
  • 44 C16MRSF2 (16 MHz clock descriptive label instead of FCLK)
  • 45 *SELSCC (indicate inverted signal)
  • 50 SNDRST (SNDRES) (replace PB7 placeholder)
  • 53 VIDPG2 (replace PA6 placeholder)
  • 52 *EAREN (replace EXTPDS placeholder)
  • 82 C2M (2 MHz clock for 74F257 chip select, as opposed to EN257 label)
  • 60 *HSYNC (indicate inverted signal)
  • 61 *VSYNC (indicate inverted signal)

An important point, the Reddit you've linked for a replacement RTC does indeed have a minor error, the time in seconds should be separate from the 256 bytes of PRAM.  It's worth cross-checking this source code with the corresponding source in a few different software emulators before sticking one of those chips in a real hardware system, not to mention that it still does need a bit of work as originally mentioned.  I started making a few changes in the copy in my GitHub repo with the schematics.

 

Really, both the RTC and the BBU, neither of these are hard to re-implement, it's just that... it requires a bit more understanding on the software side of affairs.

 

@Kai Robinson One important thing missing from the printed circuit board reproduction thus far: looks like you forgot the B1 reference designator.  Sure, here on 68kMLA we all know it by its much more affectionate name, the PRAM battery, but nothing quite completes the experience of removing and replacing those beasties without the unapologetic reference designator to assign an ID number to yet another nameless battery.

Edited by quorten
Note FCLK pin name difference too, SHT abrev.

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Mostly a combination of the Macintosh Classic schematic (a cost reduced SE that also uses the same BBU), and backtracing pins on the board. Sprint has this wonderful 'test' feature - click on any pin of the BBU, and you can see exactly where it goes. I'll send you the sprint layout file if you like, you can take a look yourself.

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10 hours ago, Kai Robinson said:

I got all excited....plugged it in and...the PSU is dead in my SE chassis :(

So close... I have to say I have high hopes about this.  Relating to the previous discussion about the BBU pinout, it looks like it's all correct on the actual board design, Sprint Layout's misclassification of MBRAM and ROW2 was due to the fact that these are connected to pull-up resistors.  Also, another note, I did find the SE PDS pinout and verified it was correct in my retrace of the schematic (one rename but otherwise good).

Edited by quorten
PDS verification

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On 8/6/2020 at 11:54 AM, quorten said:

Sure, here on 68kMLA we all know it by its much more affectionate name, the PRAM battery, but nothing quite completes the experience of removing and replacing those beasties without the unapologetic reference designator to assign an ID number to yet another nameless battery.

Is there a universal symbol for NO MAXELL for the silk screen layer?

 

 

edit: on a serious note, really diggin' the progress you're making on this! :approve:

Edited by Trash80toHP_Mini

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On 8/8/2020 at 9:53 AM, Kai Robinson said:

I got all excited....plugged it in and...the PSU is dead in my SE chassis :(

Thats one hell of a cliffhanger :-P

 

BTW, you sure your logic board doesnt have a short on one of the rails, keeping the SMPS from starting up? 

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There's 0v reading on the output of the PSU for anything - I think its the power switch thats broken, seeing as there was a fizzing noise coming from it...

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Aside from the fact that everything is socketed and the metal frame around the ports is missing, I can't tell that it isn't a genuine SE Logic Board!

 

But does it work?  I guess you'll have to get your PSU working first before you can find out....

 

c

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Yes, yes, loaded up with 4 MB of RAM.

 

Relating to the idea of a replacement BBU, unfortunately it's almost, not, possible.  We'd need like 74 I/O pins but best I'm seeing is FPGAs with 72 I/O in the 84-PLCC layout.  (The obsolete products with 74 I/O are there to taunt me.)  But hey, if we assume we don't need the two RAM config pins because everyone uses 4 MB, that would get us right down to 72 I/O pins.  Unfortunately, the FPGAs still don't have a compatible I/O pinout, but a circuit board modification could take care that.

 

Sure it's an interesting idea to think about, but yeah, probably more practical to polish up a solid implementation of the replacement RTC chip.

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To be fair - there's no reason you can't use an FPGA with more pins than the PLCC layout - you can just not use the PLCC socket and use a standard BGA or TQFP part - like the ReAGNUS: https://www.exxoshost.co.uk/forum/viewtopic.php?t=2828

 

Also - the chips that should probably be concentrated on first, would be the ADB Chip (the PIC16CR54) and the GLU logic chip (PAL16L8). I have the equations but the OE list is insane...

Edited by Kai Robinson

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Name     HAL16L8;
PartNo   ;
Date     2020-07-13;
Revision 0.1a;
Designer Kai Robinson;
Company  ;
Assembly ;
Location United Kingdom;
Device   g16v8a;

/* Dedicated input pins */

pin 1 = I0; 
pin 2 = PB6; 
pin 3 = IRQ; 
pin 4 = WRDATA;
pin 5 = ENBL1; 
pin 6 = PA4;
pin 7 = CLK;
pin 8 = PA3;
pin 9 = RTxCB;
pin 11 = OE;

/* Programmable output pins */

pin 12 = RTxCA;
pin 13 = OutA;
pin 14 = IPL0;
pin 15 = ENABLE_L;
pin 16 = ENABLE_U;
pin 17 = FLOPPY_WR;
pin 18 = B6;
pin 19 = FCLK;

/* Output equations */

!FCLK = CLK & !OE;
 B6 = 'b'1;
!FLOPPY_WR = WRDATA;
!ENABLE_U = !ENBL1 & !PA4;
!ENABLE_L = !ENBL1 &  PA4;
!IPL0 = !PB6 &  IRQ;
 OutA = 'b'1;
!RTxCA = !PA3 & !RTxCB & !OutA 
    #  PA3 & !RTxCB & !OutA 
    # !PA3 &  RTxCB & !OutA 
    #  PA3 & !RTxCB &  OutA;

 

That's what i pulled out of the GLU so far...makes sense, but the OE is a MESS. There must be a way to reduce them, but WinCUPL just crashes constantly.

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How did you figure them out? Just read the chip like a ROM and compiled the truth table back into equations?

That would still leave you without the OE table though and it sounds like you have that one as well just in non-reduced form.

Or was the chip actually not secured and you were able to read it with a compatible programmer?

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