LC/LCII/CC 68030 accelerator cloning

[Bolle]

In case someone wants to build themselves a 32MHz 68030 accelerator including 32K cache and optional FPU.

This design is the same used by Micromac (ThunderCache), Extreme Systems (Impact), Total Systems (Enterprise) and probably some more (Formac had comparable accelerators as well I think)

 

We are talking about this one:

 

 

Schematics:

 

 

 

GAL equations:

 

;$GALMODE MEDIUM

chip U1 GAL16V8A

i1=1 i2=2 i3=3 i4=4 i5=5 i6=6 i7=7 i8=8 i9=9 GND=10 /nc11=11 
o12=12 f13=13 f14=14 f15=15 o16=16 f17=17 f18=18 o19=19 VCC=20 

@ues 0000000000000000
@ptd unused

equations

/o19 = /f18
    + /f17
o19.oe = f15
/f18 = /i1 * i3 * i4 * i5 * /i6 * /i7 * f14 * i8 * /f13 * /i9
    + i2 * /i1 * i3 * i4 * i5 * /i6 * /i7 * f14 * i8 * /f13
f18.oe = vcc
/f17 = /i1 * i3 * i4 * i5 * /i6 * /i7 * f14 * /i8 * /f13 * /i9
    + i2 * /i1 * i3 * i4 * i5 * /i6 * /i7 * f14 * /i8 * /f13
f17.oe = vcc
o16 = vcc
o16.oe = gnd
f15 = i3 * i4 * i5 * /i6 * /i7 * /f14 * /i9
    + i2 * i3 * i4 * i5 * /i6 * /i7 * /f14
    + i3 * i4 * i5 * /i6 * /i7 * /f13 * /i9
    + i2 * i3 * i4 * i5 * /i6 * /i7 * /f13
f15.oe = vcc
/f14 = gnd
f14.oe = gnd
/f13 = gnd
f13.oe = gnd
/o12 = i3 * i4 * i5
    + f14 * f13
    + i2 * i9
o12.oe = vcc

 

 

;$GALMODE REGISTERED

chip U4 GAL16V8A

CLK=1 i2=2 i3=3 i4=4 i5=5 i6=6 i7=7 i8=8 i9=9 GND=10 /OE=11 rf12=12 
o13=13 rf14=14 ro15=15 o16=16 f17=17 f18=18 o19=19 VCC=20 

@ues 0000000000000000
@ptd unused

equations

/o19 = /i2 * /f17
    + i2 * f17
o19.oe = vcc
/f18 = i2
f18.oe = vcc
/f17 = f18
f17.oe = vcc
o16 = /i2 * /f17
    + i2 * f17
o16.oe = vcc
/ro15 := i3 * i4
    + /i5
ro15.oe = OE
/rf14 := /i2 * /i6 * /i7 * i8 * rf12
    + /i6 * /rf14
rf14.oe = OE
/o13 = /i6 * /rf14
o13.oe = /i9
/rf12 := i6
rf12.oe = OE

 

;$GALMODE REGISTERED

chip U11 GAL16V8A

CLK=1 i2=2 i3=3 i4=4 i5=5 i6=6 i8=8 i9=9 GND=10 /OE=11 f12=12 
f13=13 rf14=14 rf15=15 rf16=16 rf17=17 rf18=18 rf19=19 VCC=20 

@ues 0000000000000000
@ptd unused

equations

/rf19 := /i2 * rf19 * i3 * i4 * /i5 * i6 * /f12
    + /i2 * rf19 * i3 * i4 * /i5 * i6 * /i9
    + /i2 * rf19 * i3 * i4 * /i5 * i6 * /i8
    + /rf19 * rf14
rf19.oe = OE
/rf18 := /i2 * rf19 * i3 * rf18 * i4 * /i5 * i6 * rf15 * i8 * i9 * f12
rf18.oe = OE
/rf17 := /rf17 * rf14
    + /rf19 * rf17
    + rf17 * /rf15
rf17.oe = OE
/rf16 := /i2 * i3 * i4 * /i5 * rf16
    + rf18 * /rf16 * rf14
rf16.oe = OE
/rf15 := /i2 * i3 * i4 * /i5 * i6 * rf15 * /i8
    + /i2 * i3 * i4 * /i5 * /i6 * rf15 * i8
    + /rf15 * rf14
rf15.oe = OE
/rf14 := /i2 * rf14 * /f13
rf14.oe = OE
/f13 = gnd
f13.oe = gnd
/f12 = gnd
f12.oe = gnd

 

 

;$GALMODE REGISTERED

chip U12 GAL16V8A

CLK=1 i2=2 i3=3 i4=4 i5=5 i6=6 i7=7 i8=8 i9=9 GND=10 /OE=11 f12=12 
f13=13 rf14=14 rf15=15 rf16=16 rf17=17 rf18=18 rf19=19 VCC=20 

@ues 0000000000000000
@ptd unused

equations

/rf19 := /i2 * rf19 * /i3 * /i7 * /f13
    + /i2 * rf19 * /i6 * /f13
    + rf19 * /i6 * /f12
rf19.oe = OE
/rf18 := /i2 * rf18 * /i5 * /i7 * /f13
    + /i2 * rf18 * i4 * /i7 * /f13
    + /i2 * i3 * rf18 * /i7 * /f13
    + rf18 * /i6 * /f12
    + /i2 * rf18 * /i6 * /f13
rf18.oe = OE
/rf17 := /i3 * /i4 * rf17 * /i5 * i6 * /i7 * /f13
    + /i2 * i4 * rf17 * i5 * i6 * /i7 * /f13
    + /i2 * i3 * rf17 * /i5 * i6 * /i7 * /f13
    + i2 * /i3 * rf17 * /i7 * /f13
    + rf17 * /i6 * /f12
    + i2 * rf17 * /i6 * /f13
rf17.oe = OE
/rf16 := i3 * i4 * i5 * rf16 * i6 * /i7 * /f13
    + /i4 * /i5 * rf16 * i6 * /i7 * /f13
    + i2 * i4 * rf16 * /i7 * /f13
    + i2 * i3 * rf16 * /i7 * /f13
    + rf16 * /i6 * /f12
    + i2 * rf16 * /i6 * /f13
rf16.oe = OE
rf15 := /i2 * /i3 * /i5 * /i7
    + /i2 * /i3 * i4 * /i7
    + /i6 * i7 * i8
    + i6 * /i7 * i8
    + /i6 * /f12
    + /i6 * rf15
    + rf15 * /i7
    + /i2 * /i6
rf15.oe = OE
rf14 := /i2 * /i4 * /i5 * i6 * /i7
    + i2 * /i3 * /i5 * /i7
    + /i6 * i7 * i9
    + i6 * /i7 * i9
    + /i6 * /f12
    + /i6 * rf14
    + i2 * /i6
    + /i7 * rf14
rf14.oe = OE
/f13 = gnd
f13.oe = gnd
/f12 = gnd
f12.oe = gnd

 

;$GALMODE REGISTERED

chip U14 GAL16V8A

CLK=1 i2=2 i3=3 i4=4 i5=5 i6=6 i7=7 i8=8 i9=9 GND=10 /OE=11 f12=12 
f13=13 o14=14 o15=15 o16=16 rf17=17 rf18=18 rf19=19 VCC=20 

@ues 0000000000000000
@ptd unused

equations

/rf19 := i2 * /rf19 * i3
    + rf19 * i5
rf19.oe = OE
/rf18 := i2 * i3 * /rf18
    + rf18 * i5
    + /rf19 * /rf18
rf18.oe = OE
/rf17 := /rf17 * f13 * /i9
    + /i4 * rf17 * /i5 * /i6 * /i9
    + /rf17 * i6 * f13
    + /rf17 * i5 * f13
    + i4 * /rf17 * f13
rf17.oe = OE
/o16 = /i2 * /i4 * i9 * f12
o16.oe = vcc
o15 = i7
o15.oe = rf18
o14 = i8
o14.oe = rf18
/f13 = gnd
f13.oe = gnd
/f12 = gnd
f12.oe = gnd

 

 

;$GALMODE REGISTERED

chip U17 GAL16V8A

CLK=1 i2=2 i3=3 i4=4 i5=5 i6=6 i7=7 i8=8 i9=9 GND=10 /OE=11 rf12=12 
rf13=13 rf14=14 o15=15 o16=16 f17=17 o18=18 rf19=19 VCC=20 

@ues 0000000000000000
@ptd unused

equations

/rf19 := /i2 * rf19 * /i7 * i8
    + /rf19 * /f17
    + /rf19 * /rf12
rf19.oe = OE
/o18 = /rf19 * /f17 * rf12
o18.oe = /i3
f17 = gnd
f17.oe = rf19
o16 = /i4 * i5
o16.oe = /i3
o15 = /i4 * i6
o15.oe = /i3
/rf14 := /i3 * /i7 * i9
    + /rf14 * i9
rf14.oe = OE
/rf13 := /i3 * /i8 * i9
    + /rf13 * i9
rf13.oe = OE
rf12 := /i3 * i4 * /f17 * /rf12
    + /rf19 * rf12
rf12.oe = OE

 

 

For the SRAM you want 8k x 8 static RAM. The two TAGRAMs need to be 8k x 8 as well like IDT 71B74 or ATT7C174.

The other parts should be self explanatory.

 

I did not yet build any actual clones due to the lack of machines to put them into, however the GAL formulas are tested and do work.

If someone is up to the task of funneling the functions inside those 6 GALs into one modern-ish PLD let me know (like how would I start with an approach at this?)

I might have some more projects like this in the drawer that could need this sort of work.

[LaPorta]

I could only wish that any of the above made any sense to me. Not sure how you do it!

[dr.diesel]

2 hours ago, Bolle said:

I might have some more projects like this in the drawer that could need this sort of work.

 

On an accelerator side note, wonder what it would take to get one of these Amiga Vampire 600 V2s working on an 040 machine?

 

https://wiki.apollo-accelerators.com/doku.php/vampire:v600-v2:start

 

Did anyone make an 040 socket (not PDS slot) cache expansion card?  I'd like to re/create one of these for my Q605.

[Unknown_K]

The only 040 socket upgrades I know about with cache also had an overclocked 040 CPU on top. You could buy one of those to recreate the cache and then just put the CPU back on top.

[Trash80toHP_Mini]

Fabulous work you've done over the years, Bolle.

 

edit: oopsie, posted wrong tangent.

Edited November 7 by Trash80toHP_Mini

[dr.diesel]

3 hours ago, Unknown_K said:

The only 040 socket upgrades I know about with cache also had an overclocked 040 CPU on top. You could buy one of those to recreate the cache and then just put the CPU back on top.

Thanks, I'll have to find one of those.

[techknight]

I need this, but for the 68000. Would like to shoehorn an accelerator into the Portable one of these years. 

[LaPorta]

11 minutes ago, techknight said:

I need this, but for the 68000. Would like to shoehorn an accelerator into the Portable one of these years. 

If you do it, I’ll buy one off you!

[paws]

I don't know much about GALs, but from those equations it looks like it's just combinatorial logic? I've been playing a bit with the Lattice FPGAs that somebody made an open source toolchain for, and if I'm reading this correctly it'd be extremely simple to implement in one of those. The syntax is a little different but you could probably translate those equations to Verilog with a bit of your favourite text munging tool.

 

There are two problem with picking out a device: first of all, voltages, of course, since nothing modern is going to like 5V. You can still get some 5V parts, both FPGA and CPLD, but quickly glancing at Digikey, there's not really anything that has the ~90 i/o I'm counting for this board - they're mostly smaller ones. The big ones are all obsolete and very expensive. If you could accept using two or three it looks more managable, e.g. the Xilinx XC9500XL series.

 

Level shifting is of course totally doable, but at that point I'd probably start thinking about whether you want to use a real '030, and not get a perhaps slightly bigger chunk of programmable logic and stick a soft core in there. That'd make business sense, but maybe not aesthetic sense... (and that's not being snarky - I've actually spent the past few days desperately resisting the desire to make a board with a smallish FPGA and a 68SEC000, a 3.3V 68k that's still in production)

Edited November 11 by paws

[paws]

I'd love to hear about these projects you allude to btw.

[trag]

1 hour ago, paws said:

There are two problem with picking out a device: first of all, voltages, of course, since nothing modern is going to like 5V. You can still get some 5V parts, both FPGA and CPLD, but quickly glancing at Digikey, there's not really anything that has the ~90 i/o I'm counting for this board - they're mostly smaller ones. The big ones are all obsolete and very expensive. If you could accept using two or three it looks more managable, e.g. the Xilinx XC9500XL series.

 

Some of the Atmel (now Microchip) ATF15xx family are also still available in 5V.

 

https://www.microchip.com/design-centers/programmable-logic/spld-cpld/cpld-atf15xx-family

[paws]

Yeah, those could work as well!

 

Supposedly also some of the MAX II and MAX V CPLDs from Intel/Altera, by use of an external resisting (current limiting, I'm guessing):

 

https://www.intel.com/content/www/us/en/products/programmable/cpld/max-ii.html

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/pt/max-ii-product-table.pdf

 

https://www.intel.com/content/www/us/en/products/programmable/cpld/max-v.html

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/pt/max-v-product-table.pdf

Edited November 11 by paws

[Trash80toHP_Mini]

7 hours ago, techknight said:

I need this, but for the 68000. Would like to shoehorn an accelerator into the Portable one of these years. 

We were working on dissecting the MicroMac Performer just for that purpose along with cloning it for the original three supported machines.

 

.

Using SMT replacement CPU and suface mounted GALs it'll fit nicely. With the formulas from the Cache equipped accelerators there's room on the other side of the board for SRAM to bump it to Perforeme Plus spec..

 

[techknight]

I remember that thread, I commented in it awhile back. Anyways. 

 

I dont want to use GAL/PALs in my design, id rather use the XC9572, something more tightly integrated. 

Edited November 12 by techknight

[Trash80toHP_Mini]

1 hour ago, techknight said:

I dont want to use GAL/PALs in my design, id rather use the XC9572, something more tightly integrated.

I recall you saying something of the sort, but aren't you just implementing the same logic in a different package? I'm ready to build a 68000 socket connector adapter card for the Luggable PDS to just plug the Performer in to see what happens. Luggable is down ATM. Haven't bothered to try it yet, but the first test would be installing the driver in the PB100 to see if it bombs or not. If the extension loads (crossed out) that would be a green light to proceed with adapting it to the Luggable PDS in its stock form.

 

I'm hoping to one day miniaturize everything to the point it fits on a PowerBook 100's Processor/RAM daughtercard.

[techknight]

Similar logic, but yes. Why reinvent logic equations that already work?

 

Btw if you do that adapter, you will need to power the card externally as the internal power regulator won't hold it...

 

This makes the design tricky, one of the main reasons I want to eliminate the pals. Power consumption...

Edited November 12 by techknight