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nickpunt

Multiprocessor SE/30!

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"Scientists were so preoccupied with whether they or not they could, they didn't stop to think if they should"

 

1442184852_IMG_4757(1).thumb.jpg.61205fbb3df649276a7edf72c4709f35.jpg

 

 

In all seriousness though, has anyone ever attempted to put two accelerators in an SE/30? For example, a socketed powercache and a turbo 68040:

IMG_4768.thumb.jpg.6439fac772d7dc5d3bf8a67dc0b91f9b.jpg

 

I have no particular desire to be the first to attempt it as I don't want to see two extremely valuable parts go up in smoke, but my understanding is the Turbo040 can be enabled / disabled in software, so if this configuration worked electrically & in drivers, you could have the best of both worlds in software compatibility, given some software works better on 030s than 040s. My guess is daystar software would be rather confused by this whole arrangement, but who knows?

 

 

 

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Off the top of my head, you'd need something along the lines of RocketShare. It runs multiple processors in a 68K Mac as if they were different Macs in the same box booting off copies of the host's ROM in RAM on each Rocket. That way they can could share processing tasks with the host and each other, communicating via LocalTalk over NuBus.

 

You've got two processors (accelerators) in that pic that take control of the system bus. They shut down the Logic Board CPU and neither plays nicely with others. They act pretty much the same as a Rocket  under RocketWare in Accelerator mode.

 

@olePigeon, did you have a Turbo040 or the like and a Rocket in your IIci Running under RocketShare?

 

/Jurassic Park [;)]

Edited by Trash80toHP_Mini

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Devil's advocate-ly wise I'm not sure why this necessarily *wouldn't* work given the socketed CPU upgrade removes the original one. Presumably there's some line on the PDS connector that allows the slotted accelerator to steal control of the CPU bus generally (IE, put the socketed cpu "to sleep"); if *any* other type of PDS card uses this same busmaster line to halt the main CPU then presumably the socketed accelerator would need to honor it. Therefore... maybe it would be perfectly okay to have the socketed accelerator present with the Turbo 040 plugged in? But...
 

6 hours ago, Bolle said:

I don't think you can enable/disable the Turbo 040 in software.


This PDF seems to confirm that. The control panel has all kinds of options for dumbing down the 68040's cache to try to make it more compatible with troublesome older software, but I don't see a "disable the card entirely" button. Lacking that then all you'll get out of having the socketed accelerator present is more area for dust to settle on.

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What card is plugged into your socketed SE/30 Daystar in the top photo?

 

Although it doesn't work in a SE/30, the Daystar Turbo 601's control panel allows it to boot to 030 or the 601. I wonder if you could boot this insanity:

 

2018-11-15_15_06_11.thumb.jpg.e45fa9f0cd0b576c88042f4568e86f43.jpg

 

That is a IIsi cache card with the 601 in the pass through and an 030 50mhz going in the cache slot then into the IIci on the bench:

 

2018-11-15_15_07_06.thumb.jpg.bcfe6634f2553b904802a3fbc8f7deab.jpg

 

I am not willing to try this.  In addition, the cache card didn't engage as it was bumping into the RAM. That could be sorted with one PDS riser...

 

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20 hours ago, Trash80toHP_Mini said:

Off the top of my head, you'd need something along the lines of RocketShare. It runs multiple processors in a 68K Mac as if they were different Macs in the same box...

Note of course that the only reason Radius Rockets can do this is the card itself is essentially a whole computer with its own onboard RAM sockets, etc. When a Rocket is running as a simple "accelerator" (IE, not using RocketShare) it technically still delegates some I/O functions it can't do itself through Nubus busmastering to the onboard CPU.

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@Von the first photo is just a joke, it's a Turbo040 -> daystar IIcx adapter (fake) plugged into -> socketed daystar board. And then another daystar 030 accelerator -> micromac PDS adapter -> MacCon. I tried for maximal ridiculousness :)

 

@Gorgonops this is what I was thinking - the socketed daystar just works without any drivers or anything. 030 accelerators don't seem to modify the ROM in any way (hence they can use the ROMinator II no problem). Any non-030 accelerators both modify the ROM and have some degree of software control, and there's precedent to having software disable accelerators entirely.

 

MicroMac Carrera040 has a control panel with a switch to turn it to 'slow' which disabled the processor. In the FAQ, they state:

 

Q: I currently have a FPU installed, can I still use this FPU once I installed the Accelerator?
A: No, once the Accelerator is active, it will disable the CPU and the FPU you have on your logic board.

 

69322878_ScreenShot2018-11-15at4_21_08PM.png.3984e59e4151c1bf36677436848d0362.png

 

 

Turbo601 as @Von points out can be disabled.

 

m196192525.3.jpg.3ce796811f6b4c8c369f1d75fb58429b.jpg

 

 

Turbo040 has Daystar QuadControl you can disable application caching, PowerMath, Secondary Cache Control. Maybe all of those together would potentially just disable the accelerator entirely? Sometimes software is written in a way that doesn't explain its exact function, and QuadControl's options might be one of these situations.

 

14-2.jpg.be75628981a38ff7855f4c300a756f74.jpg

 

One interesting thing is that there's different software for 030 and 040 daystar accelerators. The 030 uses PowerCentral, while the 040 uses QuadControl. PowerCentral has two on/off switches for cache and FPU:

powercentral.jpg.92a6cd4d642c17f22d1bbb767dd88c43.jpg

 

This doesn't suggest the accelerator CPU can be disabled. In the case of the socketed SE/30 powercache, that would lead to not having a CPU at all, so probably a good idea not to have that option :) 

 

Order of operations

1. Electrical - can they be plugged in together without magic smoke?

2. CPU Bus - does the computer know which CPU to send stuff to?

3. Drivers - is it possible to change options in the 040 such that disabling those will fall back to the 030?

 

#1 my guess is it won't make smoke.

#2 seems kind of suspect. but, given only the 040 is modifying the ROM, it may mean its pointing to the 040 first.

#3 raises the question whether disabling the 040 FPU/cache falls back to the PowerCache 50mhz FPU/cache, or simply disabling both accelerators FPU/cache. Probably depends how the control panels are written. In fact, the computer may refuse to boot simply if you have both QuadControl and PowerCentral active. 

 

But I'm still hesitant to run the experiment :p 

 

 

Edited by nickpunt

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34 minutes ago, nickpunt said:

Sometimes software is written in a way that doesn't explain its exact function, and QuadControl's options might be one of these situations.

The explanation of the options in the documentation doesn't read to me like it under any circumstances completely disables the '040. (For instance, it specifically says that "030" mode means setting the '040's cache to write-through mode, "Powermath" involves a software module to substitute for some of the routines in Apple's SANE library... etc.) It may well be that whatever method it uses to put the motherboard CPU to sleep is hard-wired. IE, if the card's installed the "disable" switch is held down.

 

34 minutes ago, nickpunt said:

MicroMac Carrera040 has a control panel with a switch to turn it to 'slow' which disabled the processor. In the FAQ, they state:

 

Q: I currently have a FPU installed, can I still use this FPU once I installed the Accelerator?
A: No, once the Accelerator is active, it will disable the CPU and the FPU you have on your logic board.

I'm not 100% certain that the acellerator's CPU is actually disabled on this one either, and the wording of the FAQ is kind of nebulous. (It mixes the words "installed" and "active". Can it be "installed" but not "active"?) Are you certain that its "030" mode isn't the same as the Daystar's, IE, it actually means the 040 is running with all caching disabled?

 

34 minutes ago, nickpunt said:

b) does disabling the 040 FPU fall back to the PowerCache 50mhz FPU, and same for cache?

It doesn't look to me like the 040's FPU is actually disabled by turning off that "Powermath" option, it just changes the SANE pathways.

 

So far as I'm aware you can't use a 68881/2 with a 68040 under any circumstances other than the rarely used "memory-mapped peripheral" mode the chip also supported, so I can't imagine any circumstance under which a 68040 accelerator of any sort would make use of an FPU sitting in the socket of an upgraded machine.

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Well the Carrera040 will happily exist in an SE/30 with the IIsi adapter, remaining inactive.  But once the INIT and control panel are placed, the system bombs with an address error.

Edited by joethezombie

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@Gorgonops this reminds me of something I read the other day about the 040 and the 68882:

 

https://en.wikipedia.org/wiki/Motorola_68040

Unfortunately, the 68040 ran into the transistor budget limit early in design. While the MMU did not take many transistors—indeed, having it on the same die as the CPU actually saved on transistors—the FPU certainly did. Motorola's 68882 external FPU was known as a very high performance unit and Motorola did not wish to risk integrators using the "LC" version with a 68882 instead of the more profitable full "RC" unit. (For information on Motorola's multiprocessing model with the 680x0 series, see Motorola 68020.) The FPU in the 68040 was thus made incapable of IEEE transcendental functions, which had been supported by both the 68881 and 68882 and were used by the popular fractal generating software of the time and little else. The Motorola floating point support package (FPSP) emulated these instructions in software under interrupt. As this was an exception handler, heavy use of the transcendental functions caused severe performance penalties.

 

 

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4 hours ago, Gorgonops said:

Note of course that the only reason Radius Rockets can do this is the card itself is essentially a whole computer with its own onboard RAM sockets, etc. When a

Rocket is running as a simple "accelerator" (IE, not using RocketShare) it technically still delegates some I/O functions it can't do itself through Nubus busmastering to the onboard CPU.

Exactly, a Rocket is a "Mac" in its own right once the host ROM is copied into its RAM at which point it reboots running under either RocketShare in its multiprocessor mode or RocketWare in Accelerator mode as the only "Mac" with the host CPU relegated to I/O duty like the pair of 6502 CPUs on a IIfx board.

 

@nickpuntI figured your pic with the IIcx adapter was for shiggles and gits, but held my tongue. [:)] I think it's wonderfully over the top!

 

Interestingly, the Universal PowerCache in its adapter worries not about whether the 68030 socket on the SE/30 board is inhabited. It yanks on some line or other (ask Bolle) in the case it is and runs just fine sans mobo processor in the case that it's not. That makes the CPU socket a fabulous PDS wedge for installing a board of some kind ot other at some point.

 

Thanks for the FPU info, nick, I hadn't seen it explained that way. All I'd read was that the CoPro on the 68040 die was a less capable subset of discrete 68881/68882 function. Incompatibility was a good call, on the other side of the fence, I couldn't afford a 386DX system when CorelDraw came into vogue. So I bought a 386SX board that had a socket for the 286(?) generation FPU. Crunched every number vectorization routines and CorelDraw threw at it right nice! 68LC040/68882 combo could have kicked some serious number munching butt had Motorola not headed that combo off at the pass.

Edited by Trash80toHP_Mini

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Motorola did a bunch of obnoxious crap with the 040. Some of it, such as changing the processor bus to a type that is incompatible with the 030 and previous chips, may have been done strictly for performance or efficiency improvements rather than to preclude the use of older, cheaper support chips (though I more suspect it was the latter). Others, such as blocking the use of an external 68882 with an LC040, were done simply to prevent people from upgrading their existing LC040 chip with an external part; instead you have to buy an entirely new 040 to gain an FPU that is only mostly compatible with the 68882. Of course, since the 040 was internally clock-doubled and an external 68882 would not be (so it would be an internally 50MHz 040 redirecting instructions to a 25MHz external FPU), it would not have been an ideal solution anyway. It would have been nice if the choice was presented to the customer, though.

 

To be fair, Intel didn't really offer a 487 upgrade option for their chips either: the rarely seen 487 was a full 486DX in a special socket that simply disabled the existing 486SX (which I assume was soldered rather than socketed in these arrangements).

 

I believe the 040 could run in a multiprocessor arrangement with the use of additional Motorola support chips. Of course nobody ever really bothered with it because it was crazy expensive and required a lot of board space in addition to whatever software support was required to make it work properly.

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1 hour ago, Franklinstein said:

course, since the 040 was internally clock-doubled

No, it isn't. The 68040 takes an external clock twice the internal, not the reverse. (Like a true clock doubled chip, like the 486DX2; interestingly enough the 386DX also took a double speed clock.) Very little of the 040 effectively runs at the higher speed. This idea that it's clock doubled is the result of some very misleading advertising from Apple that quoted the raw clock input to make the later consumer 040 machines look directly comparable to the DX2, which has swept the PC world by storm by 1993-ish.

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According to the user manual (pg 7-1):

"The M68040 uses two clocks to generate timing: a processor clock (PCLK) and a bus clock (BCLK). The PCLK signal is twice the frequency of the BCLK signal and is internally phase-locked to BCLK. PCLK is also distributed throughout the device to generate additional timing for additional edges for internal logic blocks and has no bearing on bus timing. The use of dual clock inputs allows the bus interface to operate at half the speed of the internal logic of the processor, requiring less stringent memory interface requirements. Since the rising edge of BCLK is used as the reference point for the phase-locked loop (PLL), all timing specifications are referenced to this edge"

 

So a part marked XC68040RC25B receives a 25MHz clock for the bus, and a second 50MHz clock for internal use. On most Macs, the host machine typically has a (in this example) 25MHz oscillator that feeds the 040 the 25MHz BCLK signal directly and a PLL circuit of some variety doubles the clock to 50MHz for the PCLK input. On others, such as the PowerBook 5x0, the host's oscillator is 1/2 bus speed (in this example the crystal is 12.5MHz), so a PLL circuit doubles this to 25MHz for the BCLK and doubles it again to 50MHz for the PCLK.

 

Why Motorola didn't choose to advertise this clock doubling is beyond me. Maybe they didn't ask marketing. Maybe they wanted to make it easy for system designers and integrators by referencing only the bus clock. Maybe they didn't think about it. Maybe their documentation was screwy. Either way, the only chips marked as doubled are the QFP models in PowerBooks: those say 50/25MHz or 66/33MHz on them.

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6 hours ago, Von said:

I wonder if you could boot this insanity

No. Pinouts are drastically different between „Cache“ slot and PDS slot. Trying this in either the IIsi or IIci will result in shorting 5V to ground at best probably killing things in the process if the PSU doesn‘t turn off quick enough.

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4 hours ago, Gorgonops said:

I'm not 100% certain that the acellerator's CPU is actually disabled on this one either

It is disabled and control is handed over to the onboard 030.

The way the IIsi adapter for the Carrera is wired up also suggests that. /BR, /BG, and /BGACK are wired up right between the main PDS connector and the accelerator slot.

The Mac starts up with the main CPU and the C040 takes over once the INIT loads. You can see the three control lines toggling accordingly everytime you switch the C040 on and off in the CP.

 

On the Daystar adapter for the PowerCache and T040 the /BR line is tied to the GAL which disables the onboard CPU as soon as there is an accelerator present in the cache slot.

 

The DiiMo adapter for the SE/30 pulls down /BR disabling the logicboard CPU completely as well. That’s why the Mac won’t start with only the adapter in place but no accelerator installed.

 

The IIsi adapter for the T601 again is wired up different again to support switching the /BR line to enable or disable the logicboard CPU.

 

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48 minutes ago, Franklinstein said:

According to the user manual (pg 7-1)

If you check page 86, section 6.2.1 of the 486dx datasheet on archive.org it says this about the clock input:

 

Quote

... CLK's frequency must be stable for proper chip operation since a single edge of CLK is used internally to generate two phases...

IE, it seems to do something very similar to the 68040V because for various reasons it needs this higher frequency to cadence certain parts of its internal circuitry, but this doesn't effectively add up to the core being "double clocked" compared to its bus. There are a lot of nerdy arguments on mailing lists about what the significance of the PCLK/BCLK ratio *really* means in the 68040, but from everything I've seen the instruction timings of both the 040 and the 486 are based on how many "BCLKs" an instruction takes and neither CPU can do any full instructions in fewer than one.(*)

 

(I did see one discussion that claimed that there were parts of the 040's FPU that can complete instructions in a non-integer number of BCLKs, IE, that bits of it do run at full PCLK speed. But the whole CPU is not functionally on par with a DX2, which can do two of all the single-cycle instructions a DX can do in one bus cycle.)

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Did anyone ever do a 68K multiprocessor OS, for Workstations, Minis or whatnot? RocketShare isn't that kind of multiprocessor setup. It's software that sets up a cluster of additional single board computers within a host box networked with each other and the host over NuBus as I understand it. We've got that thread going on about the ultimate four proc PPC clone box. What OS/architecture first supported multiple processors in the micro world?

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"CLK's frequency must be stable for proper chip operation since a single edge of CLK is used internally to generate two phases..."

 

Obviously the 486DX2 doubles its base clock input internally, unlike the 040 which runs on two separate synchronized inputs. If the official definition of "clock doubling" is "internally doubles one input" then fine; otherwise I'm pretty sure the two sync'd inputs count because you're still ultimately operating at double the bus frequency.

 

The UM says "all internal timing" is based off the PCLK input, so I take that to mean 'all internal logic operates at PCLK,' not 'some parts are PCLK, some not.'

 

Per the UM, the 68040V is not clock-doubled; it's designed to be a very low-power chip that can clock down to 0Hz (depending on model) and completely lacks a PCLK input.

 

Anyway the term "clock doubled" refers to the speed at which the processor's transistors switch relative to the base frequency, not instruction throughput per base clock cycle. The UM doesn't break down the clock requirements per instruction so I have no idea what to go off of in that regard. In general you can make benchmark results convey whatever you want, depending on which tests were run and how optimized the tests were for specific hardware. If someone wants to show a comprehensive side-by-side of multiple benchmarks that count cycles per instruction for the respective chips, I would be interested in seeing it. That sort of thing is well outside the scope of this thread, though; we've derailed it slightly. 

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4 minutes ago, Trash80toHP_Mini said:

What OS/architecture first supported multiple processors in the micro world?

UNIX, I'm pretty sure; at least, it was the first real general-purpose OS to do so. Maybe something else architecture- or application-specific from CDC, DEC, or IBM in the olden days?

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That's an interesting question, since the history of multiprocessing is so eclectic. The CDC 6600 rolled out in 1964 (half a decade before Unix was even a gleam in Ken Thompson's eye) and sported one or two primary CPUs and ten "peripheral processing units" (smaller, simpler CPUs whose primary function was to serve up large sets of numbers for the primary CPU(s) to crunch.) From what I read on Wikipedia, the Burroughs large systems (introduced in the early-to-mid-'60s) also supported multiprocessing. Of course, VMS made clustering a byword, but that's a bit different than true multiprocessing; I'm not sure when the VAX line actually got true multiprocessor designs. (Of course, I'm also not sure when Unix got multiprocessor support itself...?)

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Enlarging the scope to a general discussion sounds like fun. I figured big iron had multiprocessing early on. ISTR the Mini designs my dad worked on at Prime in the late 70s and 80s used multiple processors and then microprocessors. Prime competed with DEC in the Mini era. The first to use multiple microprocessors as a unified, pipelined(?) CPU array would be what I was asking.

Edited by Trash80toHP_Mini

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12 hours ago, Franklinstein said:

Anyway the term "clock doubled" refers to the speed at which the processor's transistors switch relative to the base frequency, not instruction throughput per base clock cycle.

And the 68040 is not *clock doubled* in any respect even if we accept that internally it "runs" at PCLK instead of BCLK because that ratio has no bearing on how fast it operates compared to some other CPU, IE, there is no "non-clock-doubled 68040" to compare it to. IE, the phrase is meaningless when applied to it. (As noted before, the old 80386DX has a pin on it that needs a clock twice the CPU's "rated speed"; I looked up the datasheet for that as well and it doesn't seem like it does anything with that clock other than divide it, but there are some weasel words about clock phases differing between the core and the bus so... ???? I didn't build it so I have *no* idea.)


Plenty of CPUs "switch their transistors" at speeds faster than the input clock. This has been a thing for a long time. (An off-the-top of my head example which I *think* is correct is the old Motorola 6809, which had two input clocks, E and Q, which ran about 50% out of phase with each other, and some operations of the ALU and bus happen in half a phase, effectively switching  at "twice" the rated clock speed of the CPU. A more recent example is the Pentium 4: parts of the ALU operate at twice rated clock speed of the CPU. Based on this why didn't Intel call the 1.4ghz Pentium 4 a 2.8Ghz CPU?)

 

12 hours ago, Franklinstein said:

Obviously the 486DX2 doubles its base clock input internally

I was not talking about the DX2, I was talking about the plain-old 486DX, which according to the manual internally generates multiple phases from the input clock to cadence its internal guts. IE, there are parts of plain, non-doubled 486 that could arguably be said to be operating at twice the input clock. The reason I compared this to the 68040V is because that CPU doesn't have a discrete separate pin for PCLK (it only has BCLK), it generates that "double speed" internally...

 

Or, maybe the 68040V doesn't use PCLK at all. The major difference other than voltage is it's a fully static design, the original 68040 isn't. PLCK might be necessary in the plain 68040 in part to handle some sort of refresh function. My ignorant guess based on some of the diagrams in the PDF is it's used to pace the pipeline but, again, no idea, I didn't build it.

 

14 hours ago, Franklinstein said:

Why Motorola didn't choose to advertise this clock doubling is beyond me.

 

12 hours ago, Franklinstein said:

Anyway the term "clock doubled" refers to the speed at which the processor's transistors switch relative to the base frequency, not instruction throughput per base clock cycle.

If you want my guess as to why Motorola didn't advertise the CPU based on the PCLK speed it's because they didn't think that *is* the CPU's effective speed. (And perhaps they also thought rating it at that speed would invite negative comparisons to the 80486... because if they counted instruction cycles in PCLKs instead of BCLKs the minimum cycle time would be 2, not one. I can just imagine the articles ripping them for that. "The 68040 claims to run at twice the clock of an equivalent 486, but the truth is more complicated than that...". If you have any doubts this would be the case, well, when the DX2s came out every PC magazine on earth was chomping at the bit to benchmark the 50mhz DX2 against the non-clock-doubled 50mhz DX and give their hot take on how the DX2 wasn't *really* a 50mhz processor.) Here is a manual that has the instruction timings in it:

https://www.slac.stanford.edu/grp/cd/soft/vxworks/doc/cpu/vme/68k/mc68040/M68040UM.pdf

 

The section that explains that all timings are in BCLKs is in section 10-4.(**** see below) And again, the minimum time is "1". (Note in some of the boxes where you see "1/2" that's not half a clock, that's either one or two clocks depending on some factor, like data word length.) The 486 also does some instructions in one clock cycle. Therefore whether you declare the standard 68040 as running at twice the speed of its bus or not it's effectively running at the "same IPC", where C==bus clock, as a non-clock-doubled 486.
 

12 hours ago, Franklinstein said:

The UM doesn't break down the clock requirements per instruction


(***** Actually, the thing I linked to is the same users manual you linked to, and the same information is in section 10. Use your link, it's not a terrible scan. To quote it now that I can copy-paste:

Quote
The instruction timings are based on the following suppositions unless otherwise noted:
 
1. All timings are related to BCLK cycles and are for BR = An or suppressed. For BR =
PC, 1 and 1Lclocks to the <ea> calculate and execution times unless otherwise
noted. For memory indirect postindexed with suppressed index — ([bd,BR],Xn) or
([bd,BR],Xn,od) with Xn suppressed — times are the same as for memory indirect
preindexed with suppressed index — ([bd,BR,Xn]) or ([bd,BR,Xn],od) with Xn
suppressed.

 

The word "PCLK" appears nowhere in section 10, and therefore no instruction timings are in PCLKs.)

 

12 hours ago, Franklinstein said:

In general you can make benchmark results convey whatever you want, depending on which tests were run and how optimized the tests were for specific hardware.

I'm not saying that the 68040 and 80486 necessarily "ran at the same speed", there are plenty of benchmarks out there that suggest that the 68040 was faster in the real world at least some of the time. (Again, though, you rapidly fall into a deep, deep rabbit hole with arguments about whether contemporary benchmark X is valid because reasons, etc.) It may well do a *lot* of things faster than the 486, we all know that counting Mhz is a terrible way of comparing different CPUs to each other. But I still think it's fair to throw a flag on that whole "clock doubled" claim, for two reasons:

1: Motorola never rated the CPUs based on their PCLK input, and:

 

2: Apple didn't start calling the 68040 a "66/33mhz" CPU until after the DX2 came out; They slapped that designation on the low-end Quadras and Powerbooks that were competing against genuinely clock-doubled 486s and it misleadingly makes it look like those computers have a different CPU than the original "33mhz" Quadras, which any benchmark will show you is not true. In other words, it was a disingenuous marketing ploy. If the 68040 is indeed faster than its "rated" speed vs. a 486 the correct course of action would have been to do the whole "Mhz Myth" thing they later invented for the G4.

Ask any Commodore fanatic and they'll talk your ear off about how the 1mhz 6502 in a 64 is "faster" than the 4.77mhz 8088 in an IBM PC, and they'll have a leg to stand on because the 6502 can execute some of the simplest of its (relatively small repertoire of) instructions in... 2? clock cycles while it takes an 8088 something like 8-11 cycles to do anything. A better way to talk about CPU performance is instructions per second, of course, but that's misleading because it matters muchly what instructions you're talking about. (The 8088 has a much larger instruction set than the 6502 and it *can* do some operations faster with a single instruction than the equivalent loop of instructions for a 6502.) If you want to say the 68040 is "more efficient" than the 80486 based on instruction counts or whatever that's legit. But that "clock doubling" thing is completely a red herring.

 

12 hours ago, Franklinstein said:

That sort of thing is well outside the scope of this thread, though; we've derailed it slightly. 

That is indeed true.  I just get riled up when people mention that "clock doubling" thing. ;)

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