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Franklinstein

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About Franklinstein

  • Birthday January 20

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  • Gender
    Male
  • Location
    Tokyo, Japan
  • Interests
    Macs, Japanese cars, disco

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  • OCCUPATION
    Network infrastructure technician

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  1. Franklinstein

    Apple PHX 100

    You mean this, copied straight from the 5200/6200 Dev Note: Yes it says the 68040 bus is 32 bits "wde", and that L2 cache is attached to the 603 bus and helps to "optomize" system performance. Typos and omissions aren't exactly foreign to these Dev Notes. Note my previous observation that there are exactly zero references to the system bus speed, only to processor internal clock and the 16MHz of the CS/LC PDS slots. It doesn't mention system RAM speed either. Did you read previously where I noted that there existed ZERO 603 processors that could run at 1:1 processor:board speed exceeding 66MHz? I linked the 603 UM. It's not that many pages. That alone should be enough of a clue that anything physically external to the 75MHz processor on a 6200 is running at a lower rate, specifically no greater than half of that (which is 37.5, if you're curious). Or maybe the fact that absolutely no Apple support chips produced in 1995 ran faster than about 50MHz, including Capella? Even if it did, there's the fact that neither the L2 chips or Capella changed with the increase to 100 or 120MHz 603e models. If the faster 603e chips ran their external L2 caches at 100 or 120MHz, why did they use exactly the same L2 cache modules from the 75MHz models? Were they somehow upward compatible with a >25% increase? And why did the faster 603e require a heatsink while Capella, now supposedly also running at 100 or 120MHz, didn't? It's because everything outside of the processor on the new models ran at 40MHz while the 603e ran at a multiple of that (2.5 or 3x) internally. Again, according to the documents from Motorola, there were exactly zero 603 or 603e chips that could exceed a 66MHz bus. Go boot a 52/62/53/63xx, run TattleTech/Newer Gauge or Clockometer/Speedometer/Metronome/whatever and tell me what speed it has the system bus and L2 caches. I guarantee it's 37.5 on the 75MHz models and 40 on the 100/120MHz models. Anyway going through my cache of Dev Notes, I don't have one for the 6300, only the 5260 which is basically the same as far as the board is concerned: it runs the 100MHz 603e instead of the 75MHz 603. I don't have any Dev Notes for any machines with the 120MHz 603e or the latest variants with soldered ROM and vacant L2 cache slots. These things don't have the greatest documentation. I'll concede the CS/LC PDS thing as being a rare perfect storm, if it happens at all; I've never tried it because I have few non-Ethernet LC PDS cards. However, as you noted with the CS Ethernet and IIe card where "Apple says it won't work", I'll assume this is because the CS and LC PDS slot share the same 030 bus and only one can be active at a time. So basically choose one and forget the other (excepting CS modems, which are basically serial pass-through devices not on the 030 bus). Not that there were a ton of options outside of networking anyway.
  2. Franklinstein

    PB 2400c USB: cannot boot with card installed

    I generally remove cards on boot anyway, unless they're used for booting (which USB isn't on something that old). The 2400 (and 3400 on which it's based) is not supposed to have CardBus so there are probably some software routines that don't run properly. I don't consider it a problem big enough to find a solution.
  3. Franklinstein

    Boxed 4400/200

    Yeah I guess their marketing team decided that Vimage had brand recognition outside of Japan or something, so Interware used that name on their processor upgrades sold overseas (previously it was specifically applied to their video cards, while their processor upgrades were sold under the Booster name). I prefer OS 8.6 to 8.1 for a number of reasons, but the main reason to use it here is the FW/USB combo card which doesn't have support on 8.1.
  4. Franklinstein

    Dual 600MHz Cube

    The only chip that is pin-compatible with the 7400/7410 is the original 750, and that would be a step backward. All of the later 74xx series chips are different either because they use on-die L2 cache or they have on-die L2 plus external L3 cache; in either case the pins are different not only from each other, but from the preceding 7400 models. Also, as mentioned, the later chips have a different and greater power requirement that would need addressed even if you could physically mount them. So it looks like the maximum speed with a 7410 is going to be about 600MHz.
  5. Franklinstein

    Apple PHX 100

    Actually, nowhere in that entire Dev Note does it mention system bus speed, so I can understand where there may be some confusion because of this omission; totally Apple's fault here. This is amended in the later 6300's Dev Note (again, the guy's using the 6200's Dev Note to talk about the 6300) but for reference, the 52/62xx uses a 37.5MHz system bus. This bus clock, provided by a single oscillator and central clock generator chip, is used by the processor for its external transactions (internally it is clocked at 2x bus), and it is also the base clock for Capella and F108 and by extension the L2 cache and system RAM. The clock generator chip provides Primetime with a separate 16MHz clock to run the CS/LC PDS slots, in addition to various other clock frequencies used throughout the system. According to Motorola's user manual for the 603, this is a non-standard and unsupported configuration: the 603 is designed to only run at 1, 2, 3, or 4x bus speed, with a variety of supported bus speeds. However, 37.5 is not one of them; the 75MHz part is designed to be run at 3x a 25MHz bus. while the fastest 1:1 speed available for the 603 is 66MHz. In addition, no Apple support chips in existence at that time could operate beyond 50MHz, let alone up to 66MHz. If they did, don't you think the 9500 would operate at the same speed? Why would their flagship have slower parts than their cheapest machine? Anyway the later 53/63xx is the same except it has a standard 40MHz system bus and now the 603e supports half multipliers, which is how we get 100MHz clocks from a 40MHz base (40x2.5). The rest of the clocks and Primetime's operation are still the same.
  6. Franklinstein

    Apple PHX 100

    Small correction regarding full-speed external caches: It could technically be argued that the Pentium Pro uses an external cache, because the cache and CPU are built individually on two separate dies, but I contend that it doesn't: this cache is built in the same process as the CPU and the two are ultimately bonded together in the same processor module. They are intertwined to such a degree that any error in bonding or in either die rendered the entire module as scrap; it couldn't be reworked, unlike a faulty memory module mounted externally. Thus, I define the PPro's cache as internal. The Slot 2 Pentium II and III Xeons used a similar approach: the CPU and cache modules are both built on the same process as the CPU but this time all of the chips are attached to a carrier board on a special full-speed cache bus. These are proper external caches running at full processor speed, but nothing else in the system is on this bus or runs at this speed except the L2 cache; everything else is accessed by the 100MHz FSB (the later 133MHz FSB PIII Xeons use small on-die L2 caches, negating the argument and ultimately the need for a slot-based processor). Regardless, both processors were targeted at the maximum performance money-is-no-object end of the IT field and both ended up in a variety of Top 500 Supercomputers (such as Sandia's ASCI Red) while the 603 was used in zero, so I wasn't totally inaccurate.
  7. Franklinstein

    Apple PHX 100

    Try running a 68k version of MacBench on the 6100 and original 62xx for comparison. The only valid complaint against these machines is that 68k emulation suffered on the 6200 compared to its contemporaries or successor models, and if MB4 is a fat binary or PPC native you won't not notice the effect with a native PPC comparison with the 6100. Nothing outside of supercomputers ran external cache at CPU speed, ever, at least not once CPU speed started to decouple from bus speeds in 1990-something. No way Apple was going to pay for 100MHz SRAMs for a bargain basement computer. If they could even get 100+MHz SRAMs in 1995, they would have put them in the 9500. Guess what? They didn't: the 9500 ran its L2 between 40 and 50MHz depending on processor bus speed. All Apple L2 caches ran at logic board bus speed until the 9600/300 and 350, which had specially designed processor cards that ran the onboard L2 cache at 100MHz (while ignoring the slower logic board cache), which is still far less than the 300/350MHz of the processor clock. Then of course there were the G3s and G4s with backside caches, and those never ran faster than 50% of clock speed, usually less. The whole point and largest benefit of an L2 cache is to have low-overhead SRAM memory (read: no refresh cycles required) available directly to the processor without having to go through/wait for other chips or narrower buses to get there. The 603 processor can only talk to external devices including L2 cache at logic board bus speeds, especially since not only is L2 directly on the 60x bus in these machines, but so is the ROM and Capella, and I guarantee none of those are capable of 100MHz operation. As for a bottleneck between CS and LC PDS? I never said this was an exclusive problem for the 6200; it affects anything with Primetime including the Q630 and LC 575. Two networking cards could be problematic, if it was even possible to use legacy Mac OS simultaneously on two different domains or network types. Or CS Ethernet and a PDS video card. Or on the 575, CS Ethernet and a IIe card. It's not likely a problem anyone would encounter often, but there's the potential for degradation if both slots were active simultaneously, especially since they're both only 16MHz slots that may share the same '030 bus (the dev note isn't terribly clear if it's two '030 buses or one shared) and the Primetime has other things to do in addition to managing both expansion slots. My point was that there were a few errors or omissions in the guy's page, not that every word he typed was wrong; its still better than the LEM BS.
  8. If you notice from the above diagram, all of the boards referenced are PCI-based, both Alchemy (EDO boards, 3.3v always required from harness) and Gazelle (225MHz+ boards, 3.3v in question). Since both types of boards work in the same chassis, the harness must always supply 3.3v to the logic board. This su