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trag

68030
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Everything posted by trag

  1. trag

    Full 68040 for Quadra 605

    Thank you for the wayback link. I was looking for that page the other day and it's gone in the original. I also have used that method successfully. I just always wondered why the straight resistor swap failed. Here's a thought. I wonder if the original author of that article ever tried the resistor method of overclocking, after replacing the MC88920 with an MC88916DW. It's possible that his original MC88920 wouldn't support distributing 40MHz, but did support 36 or 38. I think this bears some experimentation. My hypothesis is that the simple resistor method actually works, if the clock buffer will run at 20/40. The clock buffer is the MC88920 or the MC88916DW, not to be confused with the clock generator. The clock generator chip ( 343S1135 ) is the one that hte resistor swaps affect. As different resistors are installed, it outputs different frequencies. Presumably, R93 is in line with the output pin of the clock generator chip. But that's all a hypothesis. It needs testing. John, have you done the clock buffer swap? I ask, because I'm wondering if there's much difference between the MC88916DW70 and MC88916DW80 in practice. I have a small supply of the latter. I also have a reel (996 pieces) of MC88916DW55 I picked up for next to nothing. It would be nice if they were like the 68040 and the speed markings weren't really all that limiting.
  2. The M suffix means it is a Macintosh card. The Acard products are bootable on the Mac. They're pretty solid.
  3. trag

    Baroni’s Collection

    Once the SIMM sockets are on an upgrade it's an open question. The CPU just puts out addresses and Read/Write signals (and a bit more bus mananagement cruft). The memory controller logic determines how many SIMM sockets are supported and of what capacity. Does that MacRescue upgrade have a 68000 on board or is it just memory and some extra logic? It doesn't seem to make sense that there would be six sockets and then not support having six SIMMs installed. But it might not support 6 X 1MB.
  4. I bet there was a Mac model with an LC PDS slot that needed a backplate and wiring harness to reach the backplane. Maybe the Classic II or Color Classic. The removable DB-9 connector would have allowed the connection of a harness and back plate.
  5. trag

    Full 68040 for Quadra 605

    John, maybe you can answer this. I've never understood it. Why does the Q605 upgrade to 40MHz require the addition of a 20MHz oscillator. Why is it not sufficient to just set the resistor pattern for the clock generator to the 20/40MHz setting?
  6. trag

    Baroni’s Collection

    Are you sure the MacRescue supports a RAM Disk? The Newlife upgrades did not. They had eight SIMM sockets for versatility, but the largest RAM configuration was 4 MB, no RAM Disk. It's hard to remember what RAM prices were like back then, but there was a period when 256KB SIMMs were almost free, and 1MB SIMMs were still $100+. So one could save a bit by installing the NewLife upgrade in a 512KE and then using six 256K and two 1MB SIMMs to get 4MB total. I think 4 X 1MB was also an option, but that then ignored the 512KB on the logic board.
  7. trag

    ABD Keyboard and Mouse Options?

    Wandering a bit from the current track of the thread, this is my current favorite ADB mouse: https://www.amazon.com/Kensington-64475-Mouse-Box-Mouse/dp/B000052WM6 I was using a second generation (tear drop) Apple ADB mouse and before that I was using a NeXT ADB mouse. Both of them picked up crud on the rollers way too often. Even when using them with a 3M Precise Mousing Surface. I don't know if it's luck or good engineering, but the Kensington rollers don't seem to gum up. The teflon pads on the bottom do collect crud (perhaps protecting the rollers) but it is easy enough to remove that every so often with a fingernail. Also, the Kensington has a heftier weight to it. It feels more like the old Mac Plus mouse in terms of weight, instead of the featherweight ADB mice. I find the extra weight makes my motions feel more precise and less strainful to hit my click points. Of course, for USB, I'd just use an optical mouse, but for ADB, I really like the Kensington. Anyone ever make an optical ADB mouse?
  8. trag

    Daystar Universal PowerCache P33 in SE/30

    I was referring to the PowerCache/030 vs. the SE/30 Socketed upgrade. I may have misinterpreted, but I took this, " on the socketed PowerCache which uses the same GAL set. " to mean that you had determined that the PowerCache030 with the EuroDIN connector uses the same GAL set as the SE/30 upgrades which plug into the 68000 socket. Were you perhaps comparing the IIsi/SE/30 adapter(s) to the IIcx adapter in that phrase? Sorry for the misunderstanding.
  9. trag

    Daystar Universal PowerCache P33 in SE/30

    That would make sense and those (or that) Daystar engineers were pretty good. Is there some mechanism by which the cache can tell whether the SE/30 is in 24 bit mode and the cacheable space is even smaller? Or are the hardware addresses to memory always the first GB, and the memory maps documented are logical addressing rather than actual hardware addresses. That is interesting to know. How have you confirmed that the GAL set is the same? Thank you for the information. Interesting, as always. The memory controller on the IIci has some limited cache support/control ability, but I don't think it fully controls a cache, as all the caches I've seen for the IIci include some kind of programmable logic (or a big ASIC) which is probably handling BERR and such. Caches for the NuBus PowerMacs, on the other hand, seem to consist of just a TAG RAM and a regular SRAM (in the needed widths), suggesting that either the NuBus PM memory controller or the PPC601 has cache control logic actually on board. The PCI Power Macs just seem to have two sets of distinct SRAM, neither of them TAG, suggesting that the comparators have been moved to either the PPC or the memory controller. However, take the above with a grain of salt. That's my preliminary conclusions for a fairly rushed overview. I don't know when I'll ever actually trace connections.
  10. trag

    Daystar Universal PowerCache P33 in SE/30

    Hmmm. I was reading something, somewhere -- maybe in TGTTMFH -- the other day about the IIci external cache. IIRC, it said that Cache Enable is only active for memory accessess. So, the first GB of address space? It makes sense, as you don't want to cache IO operations. You can't count on I/O data remaining unchanged at a given address. Anyway, it seems like tying it low so that it is always enabled could cause problems. Unless I am misremembering which signal it was and there's some other "cache this if you can" signal. I wish I could remember it better, but I was on a binge of cache information reading. Kind of a feasibility study for adding an external cache to that pass-through upgrade I picked up for the SE/30 a few weeks ago.
  11. trag

    Bolles finds

    Thanks. That's cool. I'll have to give chapter 8 a read some time.
  12. trag

    Bolles finds

    Are the 601 and the 601v different enough that you would expect one to support 1:3 and not the other? You seem better versed on this than I am. Is it correct that the 601 (and 601v) don't synthesize their own CPU clock and must be fed both the bus clock and the internal CPU clock? It may be a failure of my imagination, but I can't think of another reason why the 3:1 cases would need the ICS9178 chip.
  13. trag

    Bolles finds

    The 601 definitely supports a 1/3 bus ratio. The PM8100/100, 8100/110, 9150/120 and Power 100 and Power 120 all used it. Oh, and the PM7200/120. Also, the Turbo601 I switched from doubling to tripling had either a 66 or 80 PPC601 on it, so it's not a 601v vs. 601 feature.
  14. trag

    Bolles finds

    Interesting. I haven't read the UT601 site in a while. Was there some indication that hte problem affected some but not all IIvx users?
  15. trag

    Help identifying NuBus RAM card. (RAM Disk?)

    Actel is another maker of FPGAs such as Altera and Xilinx. So those two large chips near the back plate are likely large expensive FPGAs.
  16. trag

    Bolles finds

    Debatable. I wouldn't do it. And you would need to have an ICS9178 chip in order to perform the speed bump, otherwise it just runs at 66. Guessing, I haven't actually read the datasheet carefully, the PPC601 doesn't generate its own internal frequency based on jumpers, but gets it from an external clock source. It's easy to generate a 2X or 1/2 clock. But generating a 3X clock is more challenging, hence the need for the ICS9178. I could be completely wrong. I really need to dig out the PPC601 datasheet, assuming I have one here somewhere. But that's what I've been assuming all these years. Otherwise, why do the clock tripled PPC601s need a special PLL/clock buffer? I hesitate to mention this as I don't want to encourage any murders, but the ICS9178 is also on the PM8100/100 and faster. I think I've seen it come up on Ali Babba or other Chinese suppliers as well. No idea if those are trustworthy. I've seen an MPC part that serves the same function, maybe on the 120MHz PPC601 CPU card for the original PowerTower (Power Computing), oh, and probably on the faster 7200s, but it is not pin compatible with the ICS9178. Instructions for switching from 2X to 3X are on Marc Schrier's Clock Chipping Home page, which is also gone now, but preserved/mirrored. (Is it mirroring if it's gone? Imaged?) However, the Turbo601 does not like to operate much outside its 33MHz bus speed. So, you can't slow down much below 96. And I'm not sure if faster will work. It didn't for me, but that could have been the limits of my PPC601 chip (rated for 66 or 80, can't remember) not the limited range of bus speed of the whole card. I know for sure it won't slow down much. It might speed up. Almost forgot, though you may already know this. Some (all?) PPC601 at 100MHz and greater operate on 3.3V instead of 5V. There was a transition there somewhere between 90MHz and 100MHz. The PCC Power 120 has a bunch of level shifters on the I/O pins because of this. ICS9178_02.pdf
  17. trag

    Bolles finds

    I think that SE/30 NIC is meant for a IIsi or IIsi/SE/30. The SE/30 would never have a use for an FPU socket. That might explain the lack of a PDS pass through. There is some discussion on "The Unofficial Turbo601 Home page" about using the Turbo601 in a IIvx. There was some kind of video problem, that led to Daystar issuing a special ROM for the card, IIRC. The Unofficial Turbo601 Home Page went down a while back, but I think it is archived, or possibly mirrored. https://web.archive.org/web/20040415145546/http://www.brinnoven.co.uk/turbo601/miscinfo.html#anchor475621 If you ever have the heat sink off, would you post the CPU's rated speed?
  18. trag

    Baroni’s Collection

    No doubt. Given the different floppy connectors of the day, I'm pretty sure the hardware versions were at least a little different too. Also, I'm not 100% certain there was a PC version; I just think I remember that.
  19. trag

    Cache Puzzlement

    In chapter 6 of the attached data book is an application note called, "SN74ACT2155/2156 Cache Enhances MC68030 Processor Performance". Someone might find it useful, or at least interesting. 1990_TI_Cache_Memory_Management_Data_Book.pdf
  20. trag

    Cache Puzzlement

    The appearance of two Performa 600s, which lack the IIvx's cache have sent me on an exploration of the art of the cache. This is a pretty good reference regarding the basics: https://courses.cs.washington.edu/courses/cse378/09wi/lectures/lec15.pdf Basically, you have two sets of memory, which are smaller and faster than the next lower level of memory. Those two sets consist of Cache and TAG RAM. They have the same number of addressing bits. In other words, if you have 32K words of cache storage, then you have 32K tags as well. When a memory request is made, a portion of the address bits is used as an address to the cache storage and to the TAG storage. This portion of the address is called the index. The remainder of the memory address is the Tag or Tag Address. The word stored in TAG memory is looked at and if it matches the remainder of the address (the Tag address), then the address the CPU tried to access is already stored in cache, and the cache contents are used. Here's my puzzlement. I've been examining some real world caches. A IIci cache is pretty straight forward. It's made of four 8K X 8 SRAM chips for cache storage, which gives you an 8K X 32 memory. IIci has a 32 bit data bus, so good so far. And it has a couple of 8K X 8 chips for TAG RAM. The 8K portions match up. The 13 bits (13 bits => 8K) of cache address plus 15 bits of TAG storage (2 X 8 - 1; 1 is used for "valid" bit) = 28 bits of cacheable address space. Which is plenty for a machine with 128MB RAM maximum and considering it's one address per word, so 28 bits address space equals about 30 bits of byte space, depending on how they wired the addresses on the cache. The IIci has 32 bit addressing. And each word in memory is 4 bytes (2 bits to address) wide. And only 128 MB of RAM is possible (ignoring the memory map for the moment). So, in theory, one would need to deal with 128 MB => 27 bits, minus 2 bits because each word is 4 bytes wide => 27 bits - 2 bits = 25 bits of total cache address. With 8K of cache and TAG, that means that the Cache Index is 13 bits wide (8K => 13 bits). So the IIci needs a minimum of 12 (25 - 13 = 12) bits of Tag address. 13 bits of Index address, plus 12 bits of Tag address makes up the 25 bit cache address. Two 8 bit wide TAG RAMs minus a valid bit (2 X 8 -1), leaves 15 bits for the Tag address, so that's plenty and actually supports 1GB of RAM space, which I think matches the memory map. But again, 32K of cache memory means 32K TAGs or TAG words. Or in the case of the IIci 8K of Cache memory means 8K of TAG words. Okay, that wasn't my puzzlement. That was an example of how I'm not puzzled. Here's my puzzlement. I also examined a NuBus PowerMac cache. It consists of eight 32K X 8 SRAM chips, which gives the cache 32K X 64 memory. That's good. PowerPC uses a 64 bit data bus. But the Cache TAG is only 8K X 16. 13 bits of addressing, plus 15 (16 - 1) bits of tag is 28 bits, which again, is enough to cover all of the address space, wordwise. But 8K TAG addresses does not equal 32K of cache space. WTF? Are the NuBus PowerPCs using a 4 word block for every cache location? That might make sense. They could break up the address so that the lowest two address bits for the word are block index bits. Then the next lowest order 13 bits of address would be the cache index address sent to the TAG RAM. Then the 14 bits remaining would be the Tag Address compared to the TAG RAM contents to determine a hit or not. If there is a hit, then the lowest order 15 bits would be used on the Cache SRAM memory. But that would imply that every time the cache is loaded or cleared, it is loaded with 4 words at a time. Thoughts? There's no extra logic on the NuBus PowerPC cache, so it's limited to the comparators built into the cache RAM, and I guess the Bus Signal management is handled either in the chipset or on the PowerPC. On a IIci cache, logic for halting the bus while the cache housekeeping is done must live on the cache. Interestingly, on the cache for a PCI PowerPC Macintosh, there's just two sets of plain old SRAM. One set is clearly used as TAG, I guess, but it's not TAG RAM. It has no internal comparators. I'm not sure how that's working.
  21. Thanks, Bolle. That's good to know. Looking at how difficult it can be to find old TAG RAMs, I wish I had bought one of those lots of 500 L2 caches from OWC, back when. I forget what they were asking -- something like $125, or $.25 each, IIRC. I could never think of a reason why the expense was worth it at the time.
  22. I am looking for a detailed (good enough to read chip markings) image of a Mac IIvx motherboard. Images of the P600 and IIvi will not do, as it is precisely the differences, I want to see. Specifically, I'm interested in the corner/edge of the board where the Cache and Tag RAM chips are located, and possibly the underside of the same region. I would like to know what parts Apple used for the cache SRAM and Tag SRAM. Also, there are a number of empty resistor positions in the region on the Performa 600, that I suspect are populated on the IIvx. The Tag RAM will be the difficult component to locate, but there's a seller on Ebay who has tubes of 30 chips which are probably the proper Tag for sale. But I'm not sure. I'd rather confirm it before I spend the money.
  23. trag

    Baroni’s Collection

    I think there was a Thunderscan version for the PC market, so there may well be .exe software.
  24. Newegg has some MSATA drives on sale for $15.99 at the moment. I think the manufacturer is Dogfish. I know nothing about that company. Looking again, the $15.99 ones are only 32GB. There's a 64GB for $19. 128GB is just shy of $30.
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