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trag

68030
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About trag

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  • Location
    Austin, TX
  • Interests
    Model & Amateur Rocketry

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  1. I have also used the 6280M with 7.6.1. It works just fine.
  2. trag

    Daystar Universal PowerCache P33 in SE/30

    Wow. That's amazing. Great work, Bolle! Thank you.
  3. trag

    Full 68040 for Quadra 605

    Thank you for the wayback link. I was looking for that page the other day and it's gone in the original. I also have used that method successfully. I just always wondered why the straight resistor swap failed. Here's a thought. I wonder if the original author of that article ever tried the resistor method of overclocking, after replacing the MC88920 with an MC88916DW. It's possible that his original MC88920 wouldn't support distributing 40MHz, but did support 36 or 38. I think this bears some experimentation. My hypothesis is that the simple resistor method actually works, if the clock buffer will run at 20/40. The clock buffer is the MC88920 or the MC88916DW, not to be confused with the clock generator. The clock generator chip ( 343S1135 ) is the one that hte resistor swaps affect. As different resistors are installed, it outputs different frequencies. Presumably, R93 is in line with the output pin of the clock generator chip. But that's all a hypothesis. It needs testing. John, have you done the clock buffer swap? I ask, because I'm wondering if there's much difference between the MC88916DW70 and MC88916DW80 in practice. I have a small supply of the latter. I also have a reel (996 pieces) of MC88916DW55 I picked up for next to nothing. It would be nice if they were like the 68040 and the speed markings weren't really all that limiting.
  4. The M suffix means it is a Macintosh card. The Acard products are bootable on the Mac. They're pretty solid.
  5. trag

    Baroni’s Collection

    Once the SIMM sockets are on an upgrade it's an open question. The CPU just puts out addresses and Read/Write signals (and a bit more bus mananagement cruft). The memory controller logic determines how many SIMM sockets are supported and of what capacity. Does that MacRescue upgrade have a 68000 on board or is it just memory and some extra logic? It doesn't seem to make sense that there would be six sockets and then not support having six SIMMs installed. But it might not support 6 X 1MB.
  6. I bet there was a Mac model with an LC PDS slot that needed a backplate and wiring harness to reach the backplane. Maybe the Classic II or Color Classic. The removable DB-9 connector would have allowed the connection of a harness and back plate.
  7. trag

    Full 68040 for Quadra 605

    John, maybe you can answer this. I've never understood it. Why does the Q605 upgrade to 40MHz require the addition of a 20MHz oscillator. Why is it not sufficient to just set the resistor pattern for the clock generator to the 20/40MHz setting?
  8. trag

    Baroni’s Collection

    Are you sure the MacRescue supports a RAM Disk? The Newlife upgrades did not. They had eight SIMM sockets for versatility, but the largest RAM configuration was 4 MB, no RAM Disk. It's hard to remember what RAM prices were like back then, but there was a period when 256KB SIMMs were almost free, and 1MB SIMMs were still $100+. So one could save a bit by installing the NewLife upgrade in a 512KE and then using six 256K and two 1MB SIMMs to get 4MB total. I think 4 X 1MB was also an option, but that then ignored the 512KB on the logic board.
  9. trag

    ABD Keyboard and Mouse Options?

    Wandering a bit from the current track of the thread, this is my current favorite ADB mouse: https://www.amazon.com/Kensington-64475-Mouse-Box-Mouse/dp/B000052WM6 I was using a second generation (tear drop) Apple ADB mouse and before that I was using a NeXT ADB mouse. Both of them picked up crud on the rollers way too often. Even when using them with a 3M Precise Mousing Surface. I don't know if it's luck or good engineering, but the Kensington rollers don't seem to gum up. The teflon pads on the bottom do collect crud (perhaps protecting the rollers) but it is easy enough to remove that every so often with a fingernail. Also, the Kensington has a heftier weight to it. It feels more like the old Mac Plus mouse in terms of weight, instead of the featherweight ADB mice. I find the extra weight makes my motions feel more precise and less strainful to hit my click points. Of course, for USB, I'd just use an optical mouse, but for ADB, I really like the Kensington. Anyone ever make an optical ADB mouse?
  10. trag

    Daystar Universal PowerCache P33 in SE/30

    I was referring to the PowerCache/030 vs. the SE/30 Socketed upgrade. I may have misinterpreted, but I took this, " on the socketed PowerCache which uses the same GAL set. " to mean that you had determined that the PowerCache030 with the EuroDIN connector uses the same GAL set as the SE/30 upgrades which plug into the 68000 socket. Were you perhaps comparing the IIsi/SE/30 adapter(s) to the IIcx adapter in that phrase? Sorry for the misunderstanding.
  11. trag

    Daystar Universal PowerCache P33 in SE/30

    That would make sense and those (or that) Daystar engineers were pretty good. Is there some mechanism by which the cache can tell whether the SE/30 is in 24 bit mode and the cacheable space is even smaller? Or are the hardware addresses to memory always the first GB, and the memory maps documented are logical addressing rather than actual hardware addresses. That is interesting to know. How have you confirmed that the GAL set is the same? Thank you for the information. Interesting, as always. The memory controller on the IIci has some limited cache support/control ability, but I don't think it fully controls a cache, as all the caches I've seen for the IIci include some kind of programmable logic (or a big ASIC) which is probably handling BERR and such. Caches for the NuBus PowerMacs, on the other hand, seem to consist of just a TAG RAM and a regular SRAM (in the needed widths), suggesting that either the NuBus PM memory controller or the PPC601 has cache control logic actually on board. The PCI Power Macs just seem to have two sets of distinct SRAM, neither of them TAG, suggesting that the comparators have been moved to either the PPC or the memory controller. However, take the above with a grain of salt. That's my preliminary conclusions for a fairly rushed overview. I don't know when I'll ever actually trace connections.
  12. trag

    Daystar Universal PowerCache P33 in SE/30

    Hmmm. I was reading something, somewhere -- maybe in TGTTMFH -- the other day about the IIci external cache. IIRC, it said that Cache Enable is only active for memory accessess. So, the first GB of address space? It makes sense, as you don't want to cache IO operations. You can't count on I/O data remaining unchanged at a given address. Anyway, it seems like tying it low so that it is always enabled could cause problems. Unless I am misremembering which signal it was and there's some other "cache this if you can" signal. I wish I could remember it better, but I was on a binge of cache information reading. Kind of a feasibility study for adding an external cache to that pass-through upgrade I picked up for the SE/30 a few weeks ago.
  13. trag

    Bolles finds

    Thanks. That's cool. I'll have to give chapter 8 a read some time.
  14. trag

    Bolles finds

    Are the 601 and the 601v different enough that you would expect one to support 1:3 and not the other? You seem better versed on this than I am. Is it correct that the 601 (and 601v) don't synthesize their own CPU clock and must be fed both the bus clock and the internal CPU clock? It may be a failure of my imagination, but I can't think of another reason why the 3:1 cases would need the ICS9178 chip.
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