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trag

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    Austin, TX
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    Model & Amateur Rocketry

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  1. Okay. looks like Quest Components has forty-eight 600 MHz 750CX for ~$20 each. The 750cx comes in a 256 pin BGA (27mm X 27mm). Bus multiplier only goes up to 10X, which is probably why I was thinking it was limited to 500 MHz. On a 50MHz bus machine, the fastest you can run it is 10 X 50 = 500 MHz without overclocking the bus. They have some (7) 750FX at 800 MHz for $32.50. That's pretty good. 292 pin BGA (21mm X 21mm). The 750FX has up to a 20X bus multiplier. Anyone know how the 750GL differs from the 750GX? They have 81 750GL for $34.50 - $39. Same package as the 750FX and also up to 20X multiplier. The GL has a 1MB L2 cache like the GX...
  2. Yeah, the 750CX is still fairly available. Good luck finding stock of the 750FX or 750GX at a not-crazy price. I think the 750CX only goes up to about 400 or 500 MHz, but I might be wrong. I wish I had had $10,000 laying around back when the 750GX was in production. I would have picked up 100 of them.... Of course, I wish I had $10,000 laying around now too....
  3. Good voltage supply to cache chips? You've probably already thought of that, but it costs little to mention.
  4. trag

    512k Mac’s-a-Million Upgrade

    Safety devices wear out after a while. I had a 60 amp breaker in my home box start tripping. After much hair pulling and testing, determined that even with zero load it was tripping. It was fine after I replaced it. Not the same as a safety capacitor, but the same kind of thing.
  5. I think that Daystar had to do some trickery to get four processors in one slot. However, I'm pretty sure that the X500/X600 series of machines were designed with two processors per slot in mind. Pins 19, 20, 21 and 81 of the CPU slot are PBR, PDBG, PBG and PINT, respectively. Pins 55, 56, 57 and 58 are SINT, SBR, SDBG and SBG respectively. Where P = Primary and S = Secondary. Full pinout is here: https://www.prismnet.com/~trag/Apple_pinouts/CPU_Slot_Pinout
  6. trag

    Confirm IIci cache card is functioning

    Going back to the original question, I think that NewerTech's Gauge series will detect the presence or absence of the cache. It consists of RAMometer and two other utilities, one of which is oriented towards cache information.
  7. trag

    Mac 512K and floppy drive

    Back in the mid 90s I had two 400K mechanisms as brand new Apple Service Parts still in their original wraps. Both of them were frozen up, because the lubricant had turned to varnish. Just mentioning to give some idea or how prevalent it is for those old mechanisms to lock up.
  8. Gently prying the frame was the recommended installation method in at least some of the upgrades' manuals.
  9. IDSEL's are always wired to an address line. That's how PCI works. It's weird, but it makes sense. I just can't remember how at the moment, or I'd wander off into one of my long explanations. IIRC, it has something to do with holding some command lines a certain way at initialization and then walking the address lines until a slot sees it on their IDSEL line and responds. Anyway, from what I saw in the C600 riser, I think you'll find IDSEL for slot A goes to address 13, slot B to address 14, slot C to address 15, and I bet whichever pin is used for IDSEL in the comm slot goes to add 16.
  10. trag

    Demand for Performa 630CD?

    A RAM module having chips on one side or two sides does not really tell you anything definitive. The important question is whether a SIMM is single banked or double banked. Often, chips on one side corresponds with single banked, etc., but not always. IIRC, it has been well established that the x[x]63n supports a double banked SIMM in one socket and a single banked SIMM in the other socket, for boards with two SIMM sockets. For boards with a single SIMM socket, a double banked SIMM is supported. The remaining question is what size of bank does the family support? I seem to remember that folks have used 128MB SIMMs in them, indicating that a 64MB bank size is supported. Hardware-wise, 64MB/bank support requires support for 12 X 12 bit addressing in the SIMM slot. The 72 pin SIMM spec. supports 12 address lines, but not all machines that use 72 pins SIMMs support all 12 lines nor all possible addressing modes. Double banked 32 MB SIMMs, made of two 16MB banks, e.g., require 11 X 11 addressing, and so will be the maximum if the machine only connected 11 address pins in each SIMM slot. Anyway, if 12 X 12 (ROW v. COL.) addressing is supported, then 64 MB banks are supported, and the single SIMM slot x[x]63n machines support 128 + 4MB = 132 MB RAM and the two slot machines support 128 + 64 + 4 MB = 196MB RAM. Double banked 64MB SIMMs are an odd duck because they require 11 X 12 or 12 X 11 addressing and many machines don't support that mode.
  11. In any given PCI slot, Apple has traditionally (in this generation, don't know about Intel and late PPC stuff) wired all four INTs together. So there's a single unique INT per PCI slot. Every slot has it's own unique INT. So, when the interrupt manager (e.g. Grand Central on X500/X600) receives an interrupt, it knows exactly which slot it came from. So, my guess is that your PCI header on the 6400/6500 logic board runs a unique INT to each of the four INT pins in the header slot, but then runs just one of those four to each PCI slot on the riser card. So each PCI slot on the riser card gets its own unique INT from the header slot and uses that one INT for all four INT pins in the slot. They would still need to steal some unused pins in that PCI header to provide Bus Grant and Bus Request lines to each of the riser card slots. ASIDE: This actually is a terrible way to do things, because the PCI spec. includes provisions for PCI-PCI Bridges to expand one PCI slot into up to 16 additional slots. If one has installed a PCI-PCI Bridge all of its sub slots use the interrupt/interrupts available in the original slot. If the OS is expecting to identify the slot from the unique interrupt, this doesn't support the spec. very well. Apple's implementation does support a single layer of PCI-PCI Bridge, as far as I can tell, but it fails when one tries to have a bridge behind a bridge, which is also supported in the specification. I suspect this Apple bug is related to how they rely on the uniqueness of their interrupts, but I'm not certain. They should be identifying slots purely through the IDSEL system.
  12. trag

    Demand for Performa 630CD?

    Modifying the Q630 Clock
  13. Doh! Common 4MB, *72* pin SIMMs. 32 bits wide. Sorry for any confusion. Too late to edit.
  14. Nice bench setup. Do you do this kind of work for a living, because that looks like some very neat breadboard work. And, of course, there are your adventures in G3/G4 swapping.
  15. it's a worthy experiment. There's a good chance that the Valkyrie video controller won't address more than 1MB of VRAM, or that the address lines are not present, but who knows. The Hardware developer note (http://mirror.informatimago.com/next/developer.apple.com/documentation/Hardware/Developer_Notes/Macintosh_CPUs-68K_Desktop/Mac_LC_630_Quadra_630.pdf) pg. 16, says that the Valkyrie is similar to the display portion of the MEMCjr in the Q605 (1MB limit) and the DAFB in the Q700 and Q900 (2 MB?). The note also says that the video memory is plain old RAM, not any special dual ported RAM or such. Late edit: and the note says there's 8MB of address space allocated to VRAM. Doesn't mean much, but at least it's not limited to 1MB. Figure 2-2, pg. 19. One megabyte of memory, thirty-two bits wide, in 8 chips is made of 8 1Mbit chips which are each 4 bits wide. So, 256K X 4 chips, X 8. If you want to double that, then you need to find 512K X 4 chips. The pinout will be standard. 256K means that there are 18 address bits, and at least 9 address pins on each chip (addresses are multiplexed, sent 1/2 at a time). If there are only 9 address pins, then it can't be done, absent discovering an unused DRAM address pin on the Valkyrie chip. 512K X n memory chips require at least 10 address pins. However, there is a tiny bit of hope, as the 256K chips could be addressed in an 8 X 10 or 10 X 8 pattern instead of 9 X 9, in which case 10 address pins would be present. As someone else wrote, the first step should be to identify the VRAM chips and find a datasheet for them. Oh, one last thing, memory capacities of chips seemed to always increase by factors of 4, so 512K X 4 chips may not exist. You may have to go to 1M X 4. That can still work with 10 address pins though, so if there are 10 the first hurdle is cleared. It looks like I have a bunch of Oki MSM514400D 1M X 4 chips on hand, somewhere in the attic. These are also what the super common 4MB 32 pin SIMM would have usually have built out of, so you can salvage them from those too. Looking at the datasheet for the M2M514400, the chip has 20 pins in a 26 pin pattern. I.e. There are two rows of pins with room for 13 pins, but the middle 3 pins in each row are omitted. MSM514400E.pdf
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