Looking at the timing diagrams beginning on page 28, its kinda confusing a little bit.
The Synchronous read and write bus operations, I could clearly go off just the /AS /DS R/W and the /DBEN signals by themselves if you wanted to, as they ensure the address and or data is valid at the time these signals get asserted. But again, the listening MCU would have be at least 4 times the speed of the bus/CPU. I guess this is why just about every expansion card back in the day had a CPLD/FPGA or glue logic. an AVR wouldnt be bad because its a near 1 to 1 execution to clock ratio but the max speed a standard AVR goes up to is 20mhz.
The Asynchronous reads and writes are way different, have to pay attention to the falling edge of the clock to get the proper data bits. nothing really else to look for that I can see.
The Synchronous read and write bus operations, I could clearly go off just the /AS /DS R/W and the /DBEN signals by themselves if you wanted to, as they ensure the address and or data is valid at the time these signals get asserted. But again, the listening MCU would have be at least 4 times the speed of the bus/CPU. I guess this is why just about every expansion card back in the day had a CPLD/FPGA or glue logic. an AVR wouldnt be bad because its a near 1 to 1 execution to clock ratio but the max speed a standard AVR goes up to is 20mhz.
The Asynchronous reads and writes are way different, have to pay attention to the falling edge of the clock to get the proper data bits. nothing really else to look for that I can see.
