Soft ps mod for hard ps macs & apple II's

[Dennis Nedry]

I don't think it will be possible to clock the microcontroller off of the Mac's CPU clock - you will probably need to go many times faster than the Mac because there is a process involved in reading and comparing the 64ish pins (32 data, <32 address, maybe others) within the microcontroller. This will take multiple cycles, reasonably 50 or so at best I'm guessing. This is why I recommended some sort of combinational logic method, such as gates + a latch, or an FPGA. This could capture the state and then you could take your time to read the captured state in the latch.

Another problem is that taking in that many bits will more than likely require multiple reads, in 8, 16, or 32 bit increments depending on the microcontroller. Even if the microcontroller is synced to the Mac's cpu clock, the address can and will change between these reads, making it impossible to even read the complete bus contents even one single time.

If you can lock up the Mac - for example, execute an instruction that jumps to itself, it will hold the address constant. Maybe that's an option somehow.

I'm a fair bit more digital than analog as we've seen lately unfortunately...

 

[techknight]

I didnt think about that, but you are right. But i guess it depends on the type of CPU used as far as speed ratings so a clock multiplier could be used such as the ICS511. like x4 or x8 multiplier. Then code efficiency comes in. So for slow CPUs you would need a Latch at the bare minimum i guess, especially if your looking at a single write at one address and thats it.

Or.. the FPGA approach, but I dont know the first thing about an FPGA and thats why I want to avoid it like the plague. Probably the reason they used alot of HAL/PALs back in the day. I think I have a couple of GAL16V8s but i dunno nothing about those either ;-)

 

[Dennis Nedry]

FPGAs are really strange and I would avoid them in any situation reasonably possible too. They can be programmed in different ways, and one way that they can be programmed is by drawing a schematic of gates, latches, flip-flops, etc and hook those up to physical pins. Then once the schematic is programmed in, the FPGA works just like the schematic - literally. FPGA stands for "field programmable gate array". That is one of the few ways that I would consider using an FPGA. They can take a load of inputs and outputs and have thousands of gates of combinational logic in between. Combinational means no clock which means asynchronous and only gate delays, no clock delays.

No matter what we use, we would fall victim to logic traps if it is not synchronous to the Mac's processor clock. Say that you jump from this address:

1000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx

to this address:

1011 xxxx xxxx xxxx xxxx xxxx xxxx xxxx

And the shut down address is this:

1001 xxxx xxxx xxxx xxxx xxxx xxxx xxxx

Well, no 2 bits can change at EXACTLY the same time. So the jump must do one of 2 things to the address bus:

1000 > 1010 > 1011

or

1000 > 1001 > 1011

and through that logic trap, the latch can be triggered even though the address NEVER WAS really the shutdown address. The only way to alleviate this is to tap the Mac's processor clock and register the latch only during the proper edge of the clock.

 

[techknight]

Not quite understanding your logic about a trap.

 

[Dennis Nedry]

A quick Google did NOT turn anything up on "logic trap", so either it's obscure, my professor made up his own name for it, or I am not remembering the name correctly.

What I am referring to as a logic trap is a deep digital curiosity that causes random glitches. I'll try to explain it better.

Starting from the beginning, all combinational digital logic is made of gates, AND, OR, and NOT. Latches are when you introduce feedback into these gates, in such a way that you can lock onto something, for example, say we have a circuit with one input and one output, where the output starts as off. When an input turns on, the output turns on, but when the input turns back off, the output stays on because of feedback. (i.e. the output feeds back into an input.) So we have stored that information with the feedback. This storage is STILL combinational logic, it does not have to wait for any clock.

Sequential logic DOES wait for clocks though. So take the same example from above. If the input turns on and back off very quickly, and no clock pulse occurs during this time, it will be ignored. The input status only mattes during the clock pulse. The clock pulse registers the inputs. This has an awesome implication.

Say that you have 32 inputs. You change the inputs in between clock pulses, then once all of the inputs are settled down, a clock pulse occurs that finally registers all of the inputs. This is necessary because the EXACT time that each input changes is not known. They DO NOT and can not change perfectly simultaneously. This is why computers have clocks.

So say that you have these two binary inputs:

00

And you want to change the inputs to this:

11

Knowing that no two inputs can change simultaneously, the input state must technically change a couple of times to get from 00 to 11, even if it's in a trillionth of a second, and that can happen 1 of 2 ways:

00 -> 01 -> 11

or

00 -> 10 -> 11

If this process happens between clock pulses, then it doesn't matter. However, if you are ignoring the clock and using only combinational logic, you will occasionally detect 01 and 10 states when attempting to change directly from state 00 to 11. As you can imagine, when looking at lots and lots of bits, there can be lots of hidden intermediate states from one intended state to the next.

 

[techknight]

Knowing that no two inputs can change simultaneously, the input state must technically change a couple of times to get from 00 to 11, even if it's in a trillionth of a second, and that can happen 1 of 2 ways:

00 -> 01 -> 11

or

00 -> 10 -> 11

If this process happens between clock pulses, then it doesn't matter. However, if you are ignoring the clock and using only combinational logic, you will occasionally detect 01 and 10 states when attempting to change directly from state 00 to 11. As you can imagine, when looking at lots and lots of bits, there can be lots of hidden intermediate states from one intended state to the next.

Ok i knew and understood everything you have said up to this point....

What do you mean that no two inputs can change simultaneously? Thats the part I get lost at. Are you talking about the pipeline within the MCU? Reason why I ask is say you have 8 D-Flops and both are tied to a common clock latch, All inputs will latch in at the same time. +/- propagation delay. I guess the only thing that stops this from not being true is the fact that each gate could have a slightly different propagation delay from input-latch-output.

 

[Dennis Nedry]

In your example, your flip-flops are using sequential logic because of the common clock, so this problem does not affect the operation of your example. When I say no two inputs can change at the same time, I mean no two physical digital signals can change simultaneously. Say that you hooked your address bus up to a really good logic analyzer. You change the address on the bus to something very different, so that many of the address lines must change state to change to this different address.

If you zoomed WAY WAY in on the logic analyzer and looked at the exact spot where the address changed, I am saying that NONE of the address lines will EVER change at the exact same time. Voltage can not change instantly, there's always a rise time and most of all of the rise times may very well occur at the mostly the same time, but the voltage will intersect the logic threshold at a specific point in time, and that's the point in time that you're looking for. If it looks simultaneous, you have not zoomed in far enough.

So the problem that this causes is those very narrow strips of time where some but not all of the lines have changed. All sorts of different addresses will appear for extremely short periods of time. Combinational (non-clocked) logic falls victim to these things.

This is all because ...drumroll... digital signals are actually analog! :beige: At least analog with respect to time when lacking a clock. Consider Laserdiscs, they contain analog video encoded as analog lengths of 1s and 0s.

 

[Dennis Nedry]

[...] say you have 8 D-Flops and both are tied to a common clock latch, All inputs will latch in at the same time. +/- propagation delay. I guess the only thing that stops this from not being true is the fact that each gate could have a slightly different propagation delay from input-latch-output.

All of those flip flops would latch and propagate at slightly different times, even though they have a common clock input. There are no two separate points in time that occur simultaneously, whether it's a circuit or anything else that occurs at a single point in time.

Even the inputs to those flip flops, though tied together, would happen at different times because they can't be perfectly equidistant from the source of the clock pulse, and thus, the electric signal will get there at different times. The logic thresholds are also not exactly the same in any two Flip Flops. The resistance of the wire or trace running to it will never be the same. There are countless reasons why you can never rely on something "simultaneous", especially when it comes to combinational logic and these things that I call logic traps.

 

[techknight]

I understand what your saying now. I was confused before because I was understanding what you were saying in a totally different manor. But what your talking about falls into a category that I have known for years. the speed of the electron is only as fast as the capacitance and inductance of its substrate. The CPU or Bus logic may "switch" them at the same time, but they dont end up on the other end at the same time.

But this was not what my intentions were, as i am aware of this problem. Just never looked at it as a "trap". I always looked at it as life, I know to look for a clock.

Thats why we look at timing diagrams Data/Address has to be solid for specific duration of time before the clock pulse comes. Depending on the particular IC and the circuit layout. But thats why we have datasheets.

 

[zuiko21]

For the record, I think you're talking about race conditions.

Back to the original question, I'm in the most busy fortnight of my job, so there's little time for hacking :'( but I'm afraid it would be very difficult to sense the shutdown procedure without some help, either software or hardware, from the Mac itself. For the SE/30, I find bbraun's Soft-power enabling system extension perfectly acceptable for my projected switch box. Other models would likely require a different approach, though.

About the switch box, I still have to prototype it. The basic form is already designed, but I want to implement an emergency power on/off with a momentary switch operating just like that found in Mac II series, most Quadras, etc. -- don't wanna be unable to power up without a keyboard, like the CC >

By the way, your proposal of modded SE/30 PSU for soft control is very interesting... I was planning to make things as less intrusive as possible, but your idea is worth considering -- and will already supply the trickle power for my circuit!

 

[Trash80toHP_Mini]

As a casual observation of what might be another complication:

Does the Mac copy ROM into Ram Mapped to a Memory Mapping Offset at startup?

___if so, does this register shift always take place at the some locations?

___is it different for different Macs a/o Ram configurations?

Dunno, it just seemed like it may be a something to consider . . .

 

[techknight]

No, they use an overlay function. the ROM overlays RAM during the first startup procedure, For interrupts sake. Then once the ROM boots up so far, it goes back to its original spot, and the program counter advances to where ROM is supposed to be.

 

[Trash80toHP_Mini]

If the Quadra series was reading ROM from the slow-poke access time ROMs, NO WONDER my Radius 33 ran rings around them, Radius was licensed to run the Rocket with the ROM images copied into RAM on its local bus!

Did the SE/30 PDS accelerators read the ROMs across the PDS too?

Galumph . . . galumph . . . galumph . . . galumph . . . galumph . . . :

 

[Dennis Nedry]

Yes, it is called a race condition. I don't know where logic trap came from.

 

[techknight]

bingo. thats the term I was thinking of. lol. I remember using concepts like that for getting code out of protected microcontrollers.

 

[bbraun]

Here's my n00b question for the day:

There was discussion earlier about a microcontroller listening on the bus, decoding addresses and data accesses, and the problem with figuring out when to read these without having to sync clocks. I'm reading over the Designing Cards and Drivers book, and with the 030 PDS (I don't know if it exists on other machines), couldn't you use /AS to trigger reading a GPIO register hooked to the address lines, and /DS to trigger reading the corresponding GPIO register for data? That means the microcontroller needing to decode every bus access, which is high overhead, but would it work? It seems like some discrete logic to decode addresses for the microcontroller so it didn't have to decode every access could reduce the microcontroller's workload in this scenario?

Anyway, it is my understanding that when /AS is low, the address lines are valid, and the same thing for /DS and data lines, so assuming you could read in those lines before they are no longer valid, it seems like you could accomplish the goal without caring about the clock.

 

[techknight]

I dont have that book. Only book I have is designing cards and drivers for the macintosh II and Macintosh SE.

But I see your point and it does make sense. a peripheral card HAS to know when the Address/Data bus has settled and can be read.

 

[bbraun]

/AS == Address Strobe, and /DS == Data Strobe. They appear to be standard 680x0 signals, so the 68k manual should document memory bus accesses, I'd imagine. /AS should be low once the the address lines are all settled and there is a valid address on the bus, and same for /DS for the data lines.

Well, for /DS, if the R/W line indicates a read, it means the peripheral should be putting a valid address on the bus. For writes, a valid address should already be on the bus.

 

[techknight]

I wonder if /AS and /DS is bi-directional? if the CPu is doing a read from the card, the CPU would pull /AS low, then the card would output the data with the card pulling /DS low. Maybe?

 

[bbraun]

Designing cards and drivers:

Data strobe signal. During a read, /DS indicates that an external device should place valid data on the bus; during a write, indicates MC68030 has placed valid data on the data bus.

Here's the 68030 data sheet which documents memory bus access: http://datasheets.chipdb.org/Motorola/68030/MC68030.pdf

My understanding is the the bus master (the one controlling the address lines) should be the one driving the /DS signal.