Re: Ram for Plus or SE

[Everett1954]

Hi,

Is it True that you cannot use 2 or 3 chip 30 pin simms in a Plus or a SE?

Has anyone successfully used them in a Plus or SE?

Thanks,

Everett

 

[Elfen]

That depends on the RAM itself. I have had Pluses and SEs (along with my Mac IIcx/ci's) with 2 or 3 chip SIMMs, but not all of them worked. Further  more, they have to be matched, as in, if you use 1 2 or 3 chips SIMM, they all have to be 2 or 3 chip SIMMs in the bank (for the Plus and SE, that's 2 SIMMs per bank, 4 for most other machines). By matching, it has to be by the same company, same chips used, same everything.

But again, it does not always work, you would need to test them to see if they would work at all as not all will work. I spend much of last month gathering up all my loose SIMMs, pairing them up, testing them, tagging them and rubber banding them in groups so I know what works with what. I had several 2 and 3 chip SIMMs and about 1/2 of them worked on the LC and LCIII (though the LC III uses a different type of SIMM compared to the LC).

 

[Everett1954]

So basically i should just try them and have a 50/50 chance of them working.  I would appreciate it if anyone else having tried 2 or 3 chips modules in a Plus or SE would chime in with there experience also.

Everett

 

[trag]

It's an interesting question, especially since there's no clear theoretical reason why the 2-chip modules should not work.

I suspect that 2-chip modules don't sink enough current on the address or control lines and cause ringing on the bus.   Essentially, when there are only 2 chips on a SIMM instead of eight, the memory bus acts like an unterminated SCSI bus would.

 

[Gorgonops]

The reason 2/3 chip SIMMs usually don't work is because the 4Mbit memory ICs they use usually require a 1024 row refresh cycle. The Plus, SE, and Classic only supply a 512 cycle refresh. (Page 21)

If there are are indeed 2/3 chip SIMMs that work they probably do so because the ICs used on those particular SIMMs incorporates a 512 cycle refresh for backwards compatibility. This problem has come up before: the very common 4164 DRAM used during the 8-bit era came in both "native" 256 cycle and backwards-compatible-with-4116's 128 cycle versions. (There was a lot of demand for this because the very popular Z-80 CPU included a 7 bit memory refresh counter built-in; using the 256 count ICs required adding additional logic. But it doesn't just affect Z-80 machines; if you're replacing RAM in an Apple IIe I believe it's an issue with them too... in fact, the 7 bit counter chips seem to be the most common to this day.) If you have a 2 chip SIMM that works in a Plus it might be worth a laugh to try to look up the specific datasheet for the RAMs on it and see what it has to say about refresh cycles.

 

[techknight]

i have a handful of those, and tried it in the SE/30 (all I have handy) and they worked fine. 

 

[Gorgonops]

i have a handful of those, and tried it in the SE/30 (all I have handy) and they worked fine. 

An SE/30 is completely not the same thing as an SE when it come to the memory subsystem, of course...

 

[techknight]

Probably not, but I dont know the SEs design that well either. 

 

[Gorgonops]

Broadly speaking the SE is a cleaned up Mac Plus with ADB grafted on while an SE/30 is a Mac IIx/IIcx crammed onto a tiny little motherboard with a funky minimalistic monochrome video card built in. It would be sort of difficult for them to be more different, honestly.

 

[trag]

If there are are indeed 2/3 chip SIMMs that work they probably do so because the ICs used on those particular SIMMs incorporates a 512 cycle refresh for backwards compatibility.

Ah, thank you.  That's a great technical note.   I had a vague memory of having read about refresh issues, but I (wrongly) thought that it only applied to the II/IIx PAL SIMM subject.

Still, the 2-chip SIMM limitation is not so bad.  It only applies to the Plus and earlier, the SE, Classic and the II and IIx..  I guess pre-Plus don't have SIMM sockets, but the upgrades might have similar issues.

So, if you have 1M of addresses on  a memory chip, and it uses 512 refresh, that implies 9 row address bits?  Refresh is by rows, yes?   So the early machines expect their 1M RAM to be organized as 9 X 11 (row address bits X column address bits)?

Hmmm.  Seems the above is wrong, but I haven't puzzled it out yet.   I'm looking at a datasheet for the Hitachi HM511000 which has ten address pins and uses 512 refresh cycles.   It specifies A0 - A8 as refresh address input.

I can only guess that the multiplexed address rows for data don't correspond to the refresh rows, in some manner.  I thought that they always did.   To get 1M addresses, this RAM must be using 10 X 10 addressing, because there are only 10 address pins available.  Can't use 9 X 11 when there's no number 11 (or A10).   10 X 10 addressing implies 1024 rows and 1024 columns.  Yet only 512 rows are used for refresh.   Perhaps it refreshes two rows at a time?   I'm going to post this while I continue looking.  Feel free to jump in. 

I'm also ignorant of how CAS_ Before RAS_ Refresh works.   That doesn't appear to require a Row Address at all according to the timing diagrams.    Does that refresh the whole chip (all the rows) and so make the memory unavailable for a long block of time, with a corresponding long block of availability until the next block refresh?  Or is there an internal address counter which assigns a row address on a CAS_ Before RAS_? 

hm511000.pdf

MSM514400D.pdf

 

[Builder68]

Ah, thank you. That's a great technical note. I had a vague memory of having read about refresh issues, but I (wrongly) thought that it only applied to the II/IIx PAL SIMM subject.

Still, the 2-chip SIMM limitation is not so bad. It only applies to the Plus and earlier, the SE, Classic and the II and IIx.. I guess pre-Plus don't have SIMM sockets, but the upgrades might have similar issues.

So, if you have 1M of addresses on a memory chip, and it uses 512 refresh, that implies 9 row address bits? Refresh is by rows, yes? So the early machines expect their 1M RAM to be organized as 9 X 11 (row address bits X column address bits)?

Hmmm. Seems the above is wrong, but I haven't puzzled it out yet. I'm looking at a datasheet for the Hitachi HM511000 which has ten address pins and uses 512 refresh cycles. It specifies A0 - A8 as refresh address input.

I can only guess that the multiplexed address rows for data don't correspond to the refresh rows, in some manner. I thought that they always did. To get 1M addresses, this RAM must be using 10 X 10 addressing, because there are only 10 address pins available. Can't use 9 X 11 when there's no number 11 (or A10). 10 X 10 addressing implies 1024 rows and 1024 columns. Yet only 512 rows are used for refresh. Perhaps it refreshes two rows at a time? I'm going to post this while I continue looking. Feel free to jump in.

I'm also ignorant of how CAS_ Before RAS_ Refresh works. That doesn't appear to require a Row Address at all according to the timing diagrams. Does that refresh the whole chip (all the rows) and so make the memory unavailable for a long block of time, with a corresponding long block of availability until the next block refresh? Or is there an internal address counter which assigns a row address on a CAS_ Before RAS_?

hm511000.pdf

MSM514400D.pdf

9 YEARS LATER .....

Have you found anything new or learned anything else about these refresh issues?

So, in this thread, we're all scratching our heads trying to figure out how to overcome the apparent 512-row limit with newer DRAM chips. Feel free to jump in with any ideas!

 

[obsolete]

9 YEARS LATER .....

Have you found anything new or learned anything else about these refresh issues?

So, in this thread, we're all scratching our heads trying to figure out how to overcome the apparent 512-row limit with newer DRAM chips. Feel free to jump in with any ideas!

You may want to tag @trag to make sure he sees this.