68040 mhz

[zigzagjoe]

I did know about the 68060, but I'm unsure about the 040. The 060 was introduced with a nominal speed of 50 MHz up to 75 MHz, while the 040 remained stuck at 40 MHz, even in the L88 mask, despite several reductions in silicon or die size over the years. I'm not sure if this was due to its internal complexity, since it was a CICS chip and the 060 was a RISC-CISC chip. Increasing the voltage on the 040 would achieve 50 MHz without damaging it or causing electromigration?

I don't know what more you wish me to add as I laid out the salient points in earlier posts. Work-in-progress accelerator, E42K, half speed system bus. 5V. I was feeding in the base clock to the system PLL via an external signal generator but that was just to make my life easier as I tweaked.

It's important to remember that the datasheet and chip markings represent what Motorola was willing to specify the behavior of the chip at. Outside of there timings are not guaranteed, but there is nothing precluding the chip attempting to operate according to whatever clocks it receives. This is the basis of overclocking. 50mhz BCLK (100mhz PCLK) is out of spec on 68040, yes, but in application any of the later mask chips should achieve that without particular care. Several period accelerators shipped as "clock doublers" in that you installed them in a 25mhz bus system to run CPU at 50mhz. No reliability data exists but no reason to believe it would cause long term issues either.

In Macintosh applications the extended system bus usually is the limiting factor for higher clocks combined with the 040's small buffer mode. On (amiga) accelerators the small high-speed bus allows higher CPU clocks.