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For vram stw writes, I do N in a row and measure tb delta. Here is the frequency distribution (in number of cycles, tb ticks once every 8 cpu cycles on Performa 5200). We can see here the 4 element cpu-write buffer that @Snial referred to from the 52xx/62xx developer notes. When just...

I'll update here with what I found out today, my main objective is to see if I can learn something that would help make blitting faster. Basically, any of these two things would help a lot: 1. make writes from cpu to vram faster 2. make vram read fast enough that read-modify-write operations...

Thanks! I'll have to digest this a bit :D

Nice! Thanks! Great template you have created! :) OK interesting! Ghidra's analyze was not that helpful as it gets confused with the line-a traps. But after hitting D and skipping the a-line traps, I got a first initial disasm of "control". I've not done this kind of thing before, and not...

Great pointers! Thanks! I used Hex Fiend with @eharmon template: As far as I can tell, this is essentially configuration data that MacOS would use for the different video modes? I suppose the sRsrcDrvDir then points to where the driver routines are. And the driver seems to have...

I am very interested in how you got the drvr for valkyrie and reverse engineered it. In the attached photo, this is what I see on MacOS 8.5 ”system” in DRVR in resedit. Would you know perhaps which one of these would have code interacting with the Valkyrie IC? Would you have any disasm to...

I'm afraid I don't. I hope to one day get a 630 motherboard so I can use 68k as well. Feel free to shoot any questions should there be any. Would be great if we had an emulator that could emulate the Valkyrie more fully.

Thanks for finding this nugget!! Summarizing what I found that is relevant in the Valkyrie AV2 spec (pg158, and pg215): - cpu-writes goes into a 12-entry buffer [in contrast to Valkyrie that has 4-entry as Snial found - in the developer notes of 5200/6200] - when there is "free time available"...

I know the 5200 is supported by mklinux (a friend ran it on his 5200). For emulation the linux source for basic framebuffer, + emulating the behavior of a few control registers would be enough to get Marathon 2 and Valkyrie specific demos running. Had a quick peek at the source, emulation of...

Afaik, there is no way to do burst writes to vram. I can only do that with ram and indirectly (e.g. cache miss to load in cacheable ram) or directly by issuing dcbf which flushes a cacheable address. But vram is marked as non-cacheable. If there was a way for Valkyrie to dma transfer that would...

The AV2 is for 54XX/55XX/64XX/65XX, and starts of with "This device is totally new design". I have not read it word for word but it has still been useful. Good point. Comparing the most demanding with the least demanding available resolution, I only get about 5% diff on the test that writes to...

Two paths that might work but I don't think they are possible to achieve - a way to set a 30hz refresh rate - a way to turn off the 640x480x8 scan out mode since I anyway only care about the video

VRAM on performa 5200 is DRAM, 60ns, 1mb, on a 32 bit bus. I get about 21.8MB/s when I write 320x240x2 bytes (takes about 0.5M cycles, 0.5M/75 MHZ = 0.0067 => 320*240*2/0.0067/1024/102) (this is with ideal scenario of unrolled 64-bit writes of constant data). Two estimates for how much vram is...

Oh nice. Thanks. I see they "sacrificed" one machine to get the rail that the motherboard slots into. Might be the way to go.

I would like to be able to travel with a 6200/5200. And so I am thinking if one could just take the logic board, and have e.g. 3d printed case to slot it in into, which hooks its pins up to to a small PSU, and IDE cable (+CF card adapter), and a mac-vga port.[[ I saw this cool hack which has...

Hey Snial! Perspective texturing: screen x and y is proportional to 1/view_z. The texture is on the 3d triangle, and has texture coordinate [u,v] at the vertices of the triangle. One interpolates u/view_z, v/view_z and 1/view_z (as these are linear in screen space), then per pixel one need to...

From the developer notes for 5200/6200: If the P_D4-0 is the out of band way of it handling this, a fifth bit would be needed to differentiate whether it is the cache or the ROM that should answer, so that might explain the 5 bits in P_D4-0? (if it is active, which critical word, if it is L2 or...

Nice. I had a pretty good idea of L1 but I had no understanding of the L2. OK so any address with overlap of the low 17 bits will map to same index in L2, and Capella will kick out the LRU and store the upper other 15 bits in the tag ram (and update the LRU). This is very useful information...

Hey Snial, I checked a bit more in the manual for the 603. Let's first just ignore L2: A cacheable read, that is not in L1, the following will happen: 1. cpu executes the load, the MMU will say it is cacheable, and that it is not in L1. So a cache burst read will be requested on the bus...

Here you go: http://macintoshgarden.org/apps/mac-port-of-nbench-223-aka-bytes-native-mode-benchmarks