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MicroMac Performer Redux: Cloning a 68030 Accelerator for Compact Macs

Trash80toHP_Mini

NIGHT STALKER
OK, here we go, it's enough to start comparisons withBolle's board and for me to finish degubbing/verification. I hope this helps somebody visualize what's going on within the GALS of my card. To me this isn't gibberish, it's a snapshot album of the functional blocks in my visual schematic:

This is what I've got so far with color key.

Picture_001.jpg

This is the GAL Maelstrom, all the signals I've found so far that pretty much stay within the GALS

Picture_002.jpg

These are the only address line's I've found so far that are monitored by the pins of Gals on their way to the 68030

Picture_003.jpg

Likewise these are the only control line's I've found so far that are monitored by the pins of GALs on their way to the 68030

Picture_004.jpg

This is where it gets really interesting, these control lines are sucked into the whirlpool to emerge or not at is whim, in whatever form.

Picture_005.jpg

I have to nail down what's going on with /RW, found an exit (error?) but no entry point. /AS emerges with a large logical disconnect across several GALS. The 16MHz Clock for the 68030 is the major thorn in my side, we'll see.

What's really cool would be the three signals for the 68030 that the GALs synthesize from 68000 signals, where they missing entirely from the 68000 bus.

Picture_006.jpg

This is a shorthand version of everything that hits the 68030 in the Delta Schematic. The four address lines were stubbed out and labeled at the source, seeing them wend their way through the legs of the GALS was distracting.

Other than what I find by the time I'm through with the rest of U5 and done tangling with U7 and that [&*()&$#] 25MHx Crystal Can, we can pretty much assume everything else is connected 1:1 from 68000 to 68030. We'll see.

Picture_007.jpg

Speaking of crazy timings, here's what I've got so far.

Picture_008.jpg

Lemme know if this stuff is helpful or not, I've had feedback both ways in the past and I'm curious how about how the heads of others put things together/take 'em apart. This way works for me. Lets see if it works better in a series of diagrams out of Eagle broken down by function in the layers of Illustrator or the like. [:)]

 
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Bolle

Well-known member
It seems yours is only running the CPU at 16MHz then and the crystal only sets the speed of the 882. It is like that on my board as well.

As I discovered when going through the PAK/3 stuff the 68000 bus interface GALs as well as the 030 state machine GALs are different for either 16MHz or async 32-50MHz operation of the 030.

It is highly likely our two boards will be the same.

The 030 clock state machine looks like it is syncing the memory accesses of the 030 to either 68000 bus accesses using /AS_00, 030 bus accesses using /AS_30, Cache access using MAT0 and MAT2 or 030 ROM access.

It also generates the 68k syncronous bus cycle signal /CYC_00 which is fed into the 68000 bus statemachine.

In the end it generates /DSACK0..1 to tell the 030 that data is ready to be read from the bus.

The CPU and FPU clock itself are directly fed into the 030, 882 and clock state machine from a crystal can - EXTCLK in my diagrams.

 

Trash80toHP_Mini

NIGHT STALKER
Interesting, you identified the functions of GALs on you board, could you tell me the names/functions of mine so I can label them?

I'm wondering if different formulas in the 68000state machine can change the multiplier? Mine could be run at a 3x multiplier of 25MHz without changing its oddball (for a 16MHz board) 25MHz Crystal Can?

With a 50MHz oscillator, would the GALs be capable of running the CPU at 32-50(48?)MHz?

Do my functional diagrams make it easier or harder for you to see the processes than reading from a conventional schematic or about the same? I remember your diagram from the ProtoCache1 PM thread, IIRC it wasn't linear like the Eagle representations? You said something to the effect that you liked to see the flow of things(?) in a schematic tweaked to show the interactions? That schematic I could see/read a lot better than the linear Eagle type representation. Maybe it's because the only schematics I've tried to read were Apple's engineering drawings and the multiple page IIsi schematic I pieced together into one very long graphic.

U6 (68000 state machine?) is driving CLK on my board's 68030 at 16MHz, not the 25MHz Crystal Can?

 
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Trash80toHP_Mini

NIGHT STALKER
What do you think about the notion that my tiny, but very flexible (supports Plus, SE and Classic connector installations) Accelerator could be tweaked to run in the Luggable? Dropping the Plus and Classic permutations of its three way bus and only supporting a Luggable translation of the SE PDS connector for fitment would be trivial. Clocking tweaked in the GALs for the "async 32-50MHz operation of the 030" from the Luggable's 16MHz PDS/bus clock would be non-trivial, but possible?

If I can get a PerformerMini up and running in the Luggable, then a miniaturization quest to fit it on the PowerBook 100 Processor/2MB stock RAM daughterboard could ensue? That thread was the genesis of this impossible dream after all!  :ph34r:

 
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Trash80toHP_Mini

NIGHT STALKER
68000vsLuggablePDS-PINK.JPG

Luggable-PDS-Card-PhysicalSpec.JPG

SEvsLuggablePDS.jpg

LPDS-68000-DIN.jpg

Luggable-MB-Slots.JPG

SE-PDS-Connector-Pinout.JPG

That Luggable Slot is some kinda kluge, I tried a NuBus Card with the pin and row markings in it. First it was sitting backwards, plate cover to the front. Second, its pin numbering is the reverse of NuBus, but Row "A" remains on the bottom. Was anything other than the unobtanium SE PDS Card Expansion Cage interface card made for the Portable PDS?

I think I may have it sorted out now, but what a mess! Has anyone got a link to a picture of such a rare thing as this kind of unicorn poop? Got the pics set up for a good look at it when things slow down at work tomorrow.

68000 <-> Luggable PDS connections don't look too horrible, weird as all get out going by a couple of signal names, dunno.

SE PDS <-> Luggable PDS comparison comes next, If they're as similar as DCaDftMF says, that would be a good thing.

The Performer speaks SE PDS, let's see if we can get it to speak Portable PDS. Not worried about the 16M clock signal of the Portable. Looks like the GALs on my Performer might just double that 16MHz input to 32MHz on the 68030's CLK line as it presently doubles the Plus/SE 8MHz clock to 16MHz on 68030 CLK. [}:)]

Tired of buzzing connections and playing in AI for a bit. Taking a side trip into PowerBook 100 Fantasy Land, extrapolating from what might not quite be impossible dreaming for a Luggable PerformerMini. PB100 PerformerMicro would be the bombe.

 
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Trash80toHP_Mini

NIGHT STALKER
Had another look at EvilCapitalist's thread:





He posted a great shot of his SE Accelerator, looks like it may have pads (buffers and SRAM) for unimplemented Cache. Has anybody got one with the Cache on board? The first thing that struck me was the four GALs with Pads for an unimplemented (empty) PLCC socket config:

View attachment 14177

Gals config might have been the first thing on my first visit to that thread, but I've had GALs on the brain lately. :/

Third thing that struck me was that populated ASIC socket, I just HATE finding those ICs on a board! :p

 
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Trash80toHP_Mini

NIGHT STALKER
Just PM'd these questions to techknight, our resident Portable guru. But any feedback at all here would be greatly appreciated. Especially so as it will relate directly to GAL implementations:

These might be the last hardware pieces to inscrutable Performer in Luggable research posted above.

View attachment PDS-Signals_Page.PDF

The SE PDS linkage of Reset/Halt to same on "68000 IC/PDS" is clear, but on the Portable PDS it's not straightforward.

/SYS.RST Initiates a system reset.
 

It looks to me like the simplicity of the Reset/Halt linkage on SE PDS to 68000 "PDS" might be penciled in as indirectly linked to 68000 "PDS" in the Portable via connection to the Powe Manager IC so it doesn't poleaxe the system processes but acts more like: 

/SYS.PWR A signal from the Power Manager IC that causes associated circuits to tristate their outputs and go into the idle state; /SYS.PWR is pulled high (deasserted) during sleep state.

WAG: this last discrepancy between the PDS implementations might be ignored?

/DELAY.CS Input indicating that system is inserting wait states; can be used to gate chip selects.

In the system state where the 68030 on the Performer is running the show while the Portable's CPU is disabled it should be unnecessary. The only thing that makes any sense to me about that signal would be its enabling the Portable's CPU to gate chip selects on a PDS card while running the card's driver routines?

Dunno, I'm winging it here as usual, whatcha think?

edit: ignore the blue lines on the diagram in my last post, the answer to that ? was "please erase me!" but I'd highlighted the pencil lines in sharpie for the scan before I found the answer. :/

 
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Trash80toHP_Mini

NIGHT STALKER
Forgot to mention that the answer to the /DTAK - /EXT.DTAK question implied by info on the diagram probably falls into the "68000 has been poleaxed, Performer uses /DTAK internally: ignore me!" category.

edit: uses it "internally" in the process of running the I/O data acquisition bus of the Luggable on its own.

 
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techknight

Well-known member
I know the /DELAY.CS is used for the RAM on the portable as its slower than the rest of the BUS, but I forget the EXACT usage details. 

It is described in the macintosh developer notes for this model. 

 

Trash80toHP_Mini

NIGHT STALKER
Does it use another type of RAM than the PowerBook 100's PSRAM? Is PSRAM slower than SRAM and DRAM? Very strange. Here we go diving into the DevNotes again. :wacko:

I'm proceeding under the assumption that SE PDS /Reset=/Halt signal yanking on the Portable's /SYS.RST line will be andled fine by the Power Manager IC.

Does the rest of the 1:1 control line signal comparison between SE and Portable PDS slots look right to you?

 

techknight

Well-known member
I dont know, I never messed with the portable PDS, but I dont see it any different than anything else. and yes /SYS.RST is the entire machine reset line. 

 

Busterswt

Well-known member
Found this thread very interesting and was disappointed to see it drop off nearly 8 months ago! Were you all able to make any progress since February?

 

Busterswt

Well-known member
@Trash80toHP_Mini Were you able to determine whether or not the MicroMac accelerator would work without the onboard 68000? IIRC, you were looking to mate the accelerator board with the main board with a socket and 1x32 connectors rather than the Killy Clip, but maybe I misread that. 

I have the SE version of the card without the GAL at U7. Any idea what that does in a Plus/Classic and why it’s not needed in the SE?

 

Trash80toHP_Mini

NIGHT STALKER
Haven't looked at that as a possibility yet unless you can link to a specific post, If you've just read through this thread you have a much better understanding of what we were doing last winter than I do. I've yet to test my Performer, see if its drivers crash my PB100 or send it off to joe. That last should be early in the New Year after shipping channels clear of holiday returns and temps are no longer involved in the package smashing process.

 
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