It depends how many address bits exist at the ROM slot and how the G3 decides between built-in ROM and ROM DIMM slot.Is there some way to tell the host machine which of those two addresses to use? The problem, that I see, is that the host machine expects the ROM to be at a certain address, and when it is programming the ROM, it's going to use those same addresses. Or do you get to choose the address range to which it programs?
The Beige G3 schematics is missing the page containing the built-in ROM chips? At least, I know sheet 9 is missing but that's for DRAM DIMMs.
Actually, does Beige G3 have built-in ROM chips? Gossamer HW ERS says no! So maybe forget everything I've been talking about...
The G3 schematics show the ROM DIMM is 64 bits (8 bytes) wide and has 20 address bits. I think that allows for 8 * 2^20 = 8 MiB of ROM.
If there's two banks then that's 16 MiB.
The MPC106 (Grackle) manual says:
For ROM/Flash support, the MPC106 provides 20 address bits (21 address bits for the 8-bit wide ROM interface), two bank selects, one output enable, and one Flash write enable. The 16-Mbyte system ROM space is subdivided into two 8-Mbyte banks. Bank 0 (selected by RCS0) is addressed from 0xFF80_0000 to 0xFFFF_FFFF. Bank 1 (selected by RCS1) is addressed from 0xFF00_0000 to 0xFF7F_FFFF. A configuration signal (FOE) sampled at reset, determines the bus width of the ROM or Flash device (8-bit or 64-bit) in bank 0. The data bus width for ROM bank 1 is always 64 bits. For systems using the 8-bit interface to bank 0, the ROM/Flash device must be connected to the most-significant byte lane of the data bus (DH[0–7]).
If the G3 doesn't have built-in ROM, then build a ROM DIMM that is 8 MB with a switch that selects which 4MB is at the FFC00000 range for boot?
We would have to change the programmer to program the FF800000 range or use the switch while the system is running which would probably be safe only for Open Firmware and in that case we would have to make our own Open Firmware programmer anyway.


