Memory maps of 030/040 accelerators?

[ymk]

I'm looking for I/O ranges of accelerators and other popular cards that fit the 030 PDS or CPU socket.

They don't have to be detailed descriptions (though it wouldn't hurt); I want to prevent conflicts with other hardware.

I'm most interested in:

• Diimo 030 accelerators
• DayStar PowerCache 50MHz
• Interware Booster 50-SE30F

Thanks.

 

[zigzagjoe]

I'm looking for I/O ranges of accelerators and other popular cards that fit the 030 PDS or CPU socket.

They don't have to be detailed descriptions (though it wouldn't hurt); I want to prevent conflicts with other hardware.

I'm most interested in:

• Diimo 030 accelerators
• DayStar PowerCache 50MHz
• Interware Booster 50-SE30F

Thanks.

Booster - None
Diimo - Logic on board captures writes to 0x50f01f03 Bit 0 (VIA1 Port A) , Pin 5 on test connector. Write a 1 to enable cache, 0 to disable/clear.

 

[ymk]

Booster - None
Diimo - Logic on board captures writes to 0x50f01f03 Bit 0 (VIA1 Port A) , Pin 5 on test connector. Write a 1 to enable cache, 0 to disable/clear.

Excellent! Thank you.

Is there a similar cache enable register for the DayStar PowerCache?

 

[zigzagjoe]

Excellent! Thank you.

Is there a similar cache enable register for the DayStar PowerCache?

I'd assume so - but I haven't dug into how the logic on the Powercache works. However, if you take the control panel and disassemble it, it will make pretty obvious what's going on. Look for writes happening in between pairs of SwapMMUMode traps, especially if they're going to constant addresses.

 

[Bolle]

The main card select signal on the PowerCache is activated on 0x5200 0000.
It also decodes SWIM I/O address space to slow things down for proper floppy operation.

When the main select signal is active a second GAL decodes register addresses at 0x60000 (looks like that will deactivate the external cache), 0x50000 (activates the external cache) and 0xF0000 (I think that might flush the cache - it resets the cache tag SRAM)

 

[zigzagjoe]

Does powercache issue dsack for accesses? The Diimo just watches for access to the VIA bit and uses that. It also decodes SWIM, Sound, SCC ranges (somewhat coarsely) to control speed for proper operation/sound.

 

[ymk]

When the main select signal is active a second GAL decodes register addresses at 0x60000 (looks like that will deactivate the external cache), 0x50000 (activates the external cache) and 0xF0000 (I think that might flush the cache - it resets the cache tag SRAM)

Thanks! To enable the cache, would reading a byte from 0x52050000, then from 0x520F0000 with consecutive instructions work?

I'd give it a try, but I don't have one yet.