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SE/30 logicboard recreation


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This is super cool, great work.

 

Reverse-engineering even simple gate arrays is still a really intimidating idea for me, I don't think I could work up the guts to handle something that also does sensitive analogue timing.

 

I wonder why some of the original PALs aren't protected? I would assume the factory would just be banging them out on a big programming fixture and thus not have much room for variance.

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19 hours ago, ravuya said:

I wonder why some of the original PALs aren't protected? I would assume the factory would just be banging them out on a big programming fixture and thus not have much room for variance.

 

No idea. Most of the ones I have seem to be mask programmed devices. Some of them didn't even have provision for being read from/written to because they instantly died when I tried to read them in my programmer.

However there are a few that have original PAL16* part names on them with Apple part numbers stamped on. It was one of those that was not protected.

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@Bolle I'm curious what factors you think led to being able to move from a 6-layer to a 4-layer board and why Apple's engineers didn't originally go 4-layer. Was it just the improved software tooling available nowadays? Easier jumping off point already having a first revision? Manufacturing improvements? 

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On 3/17/2021 at 1:03 AM, techknight said:consolidating it into a 4-layer board is impressive in of itself. And a good starting point. 


Would a 4-layer board have lower noise immunity than the original 6? I ask because there must have been a reason to use 6 rather than 4.

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Can't tell for certain why they went for a 6 layer board back then.

I guess manufacturing back then didn't allow for the tighter tolerances you need to fit everything into 4 layers - and if it did it must have been more expensive than just having a 6 layer board manufactured which would allow for less stricter tolerances. With the trace widths/trace distances found on the original board they wouldn't have been able to fit everything on two signal layers.

 

I'd also guess that the Software used for designing the board was not the limiting factor. By the time the SE/30 was made there were powerful enough CAD solutions available.

 

 

The layer stack up on the original board from top to bottom is:

 

signal

ground

signal

signal

power

mixed signal/ground plane

 

This is a good mix between signal integrity (you have a ground plane next to each signal plane except one) and will give at least some planar capacity with the power plane being next to at least a partial ground plane on the bottom.

 

I don't know enough about this kind of analog voodoo to tell if 4 or 6 layers is going to be better regarding EMC.

Signal integrity and noise is not really a concern with the low speed signals found on a 68k Macintosh logicboard.

Following a few simple PCB design thumb rules should be enough here (as it seems - the board is working fine so far at least ;))

 

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I just noticed I didn't even try that yet - fitment check:

 

IMG_6295.thumb.jpg.3c9d95995b05ecbb65bee0ae8cba926c.jpg

 

Fits :)

 

Now on to the missing bits in the serial section and to add the remaining 4 RAM sockets.

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Posted (edited)
20 hours ago, demik said:

Did you use the DuPal tool we talked earlier for the PALs ?

 

Yes. The peeper application in live mode to toggle individual pins and observe the behavior is really useful. The automated analysis was only useful to give a few hints.

It didn't even finish on the two 16L8s because it got confused with the latches and aborts when outputs don't match what it expected them to be.

 

On the registered devices it was a good way to record truth tables of the statemachines. With that the only thing that was left was to see how the known inputs (because we have the schematics and know what's going to be an input) change the behavior of the statemachine.

 

https://imgur.com/a/cWk36uf

 

Based on the truth tables and the entry conditions for each state pattern based on the inputs it was easy to form matching equations.

Edited by Bolle
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20 hours ago, Bolle said:

 

Yes. The peeper application in live mode to toggle individual pins and observe the behavior is really useful. The automated analysis was only useful to give a few hints.

It didn't even finish on the two 16L8s because it got confused with the latches and aborts when outputs don't match what it expected them to be.

 

On the registered devices it was a good way to record truth tables of the statemachines. With that the only thing that was left was to see how the known inputs (because we have the schematics and know what's going to be an input) change the behavior of the statemachine.

 

https://imgur.com/a/cWk36uf

 

Based on the truth tables and the entry conditions for each state pattern based on the inputs it was easy to form matching equations.

 

Very interesting, thanks !

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Incidentally, I wonder if your PCB layouts would still show which pads on an original SE/30 board are connected to each other. I imagine it'd be useful for repairs/bodge writing/troubleshooting.

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Kudos! Where and how did you find the parts? Cannibalizing pin-grid-array chips is hard, and doesn’t the se/30 have some CPLDs? I spotted a VLSI Technologies (VTI) package marking.  They made ASICs, which I’m guessing here is a custom chip. 

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