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LC 1 Ram Upgrade


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Ok so all this ram upgrade talk got me intrested, i have a spare LC board lying around....

I know uniserver tried without success before, but i have some time to kill today so figured i would try

 

Removed some 512k chips from a old 8mb sim and soldered them to the LC's board, and... nothing.

It boots just fine, but dosen't see the ram, still only 2mb. Tried my LC 2's rom's and still the same

 

did anyone ever get to the bottom of why this dosen't work?

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< Laugh In >

 

V e r r r r y interesting . . .

 

< /Laugh In >

 

I can't get the url to work correctly, so enable the sidebar for the direct LC link or just whack the spacebar down to p.33 for the LC:

http://ftp.iinet.net.au/pub/apple/US/Macintosh/Utilities/memguide.pdf#page=33&zoom=auto,0,864

 

At a first guess, I'd say the LC is hobbled in hardware, not in ROM per received wisdom. Considering how memory mapping appears to be a moving target that's based upon the memory polled at startup for so many other systems, you may have a shot at it.

 

I'd buzz the connections for the SIMM slots to see which CAS and RAS lines are present there, but not implemented on the soldered memory pads.

A few jumper wires later and you just might have the world's first 16MB capable LC. [}:)]]'>

 

Take a look at the DevNote as well, for the Memory Controller ID and check that against other systems. Memguide curiously lacks mention how the bank selects are set up for the LC . . .

. . . as do some of the 4MB soldered to the MoBo hobbled systems . . . hrmmm? :?:

 

 

 

 

< . . . and my Quadras 700 & 950 have FOUR Bank Select lines! :O >

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Well, i did a little probeing, but i must admit i'm not sure what i would be looking for

The RAS line is connected to all the soldered chips (orig and the ones i added) the CAS line is connected across all the orig chips, and accross all the new chips, but the to sets are not connected together

 

Neither are connected to the simm banks

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Received wisdom: http://lowendmac.com/1990/mac-lc/

 

The LC was the first Mac to run a 32-bit CPU on a 16-bit data bus, making memory access slower than it should be (the LC benchmarks at about 3/4 the performance of the Mac II, even though both use the same 16 MHz 68020 CPU). Although Apple had retired the 68020 chip with the Mac II in January 1990, it reintroduced it with the LC that October.

 

To add insult to injury, Apple programmed the ASICs to support no more than 10 MB of RAM even if more was installed.

My pet theory is that it's not necessarily the Memory Controller (ASIC) mentioned above. Apple could well and truly have hobbled the LC by setting the traces up for the RAM so that the Column Address Select and Row Address Select lines are divvied between the SIMMs and the Soldered MoBo RAM to hold the LC down to that ludicrous 10MB figure. I'm not at all sure how the LC Memory is set up. One or two Banks of RAM . . . could be two banks of 16bit words? Dunno, my brain is fried from playing in Illustrator all day . . .

 

. . . you'll have to wade into the Dev Notes to find out if the LC's Memory Controller was used in any more capable Macs. It'd be silly to develop a crap ASIC when they could just bork the MoBo design to achieve their nefarious goal. That's the only chink I can envision in the LC's Memory limitations . . .

 

. . . or you could just wait for a real Memory guy to wade into the fray to tell you the real deal, my theory is a WAG! ;D

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Well, the way cas and ras is setup is as follows:

 

The top two original chips have cas connected together, it is not connected to either sim slot

 

The bottom two original chips have cas connected together, and is also not connected to either slot

 

The top two chips I have added have cas connected together, and it is connected to the cas pin of the SIMM slot closest to the VRAM SIMM

 

The bottom two chips I have added have cas connected together and it is connected to the cas pin of the SIMM slot closest to the power connector

 

the ras pins of all soldered chips (both orig and the ones I have added) are connected together, and it is not connected to either SIMM slot

 

The ras pins of the two SIMM slots are not connected

 

Right now I just want to figure out why it won't use the extra chips, pushing it over the normal limit would just be a bonus ;)

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Interesting thought...

I'll remove all 8 chips and see

 

I would be interested to see what happens if the orig chips where replaced with bigger ones, but I don't think I have any bigger Simms I would want cannabalise...

 

edit: the answer is no, I either get nothing (no chime, black screen) or a weird clicking noise from the speaker

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If you've got some wire wrap wire, you're good for the jumper tests.

 

Sounds like if you interconnect the ROW Address Select lines between the Soldered "Bank" and the SIMM "Bank" properly, you might see all 8MB of the soldered replacement RAM. If certain RAS lines are omitted on either end, those Rows of your Chips a/o SIMMs aren't addressable, hence, invisible!

 

Dunno, just a WAG on my part, but it's sounding more likely from I can parse in your report. Try setting up a block diagram of the LC memory setup on paper. ;)

 

Have you searched for the DevNote?

 

ARRRGH!!!!! ><img src='https://68kmla.org/forums/uploads/emoticons/sad.gif.fd4612761a7f036f230186185c887adf.gif' alt=':('>< Been there, done that, is the LC DevNote still MIA gang? :?:

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I don't have an LC, but I looked at the ROM disassembly a bit. There are definitely limitations in ROM, and from the ROM, it is likely the VISA memory decoder is limited to 10mb.

The LC entry in the table the ROM has to tell it about the machine, says there are 2 banks of RAM: one up to 8mb, and one up to 2mb. The routine that figures out how much RAM is installed in each bank assumes always 2mb in the 2nd bank.

The LCII uses the same memory controller, but has 4mb soldered on. I also do not have an LCII, but everymac says it is limited to 10mb, although you can install up to 12mb (2x4mb SIMMs + 4mb soldered), but only 10mb will be recognized. Looking at the LCII ROM, the LC's table entry is unchanged, but the memory sizing routine now detects 4mb vs. 2mb soldered RAM. So, if you changed the LC's table entry to expand the 2nd bank size up to 4mb, it might be able to detect 4mb soldered. However, that doesn't expand the total memory available. In the case of an LCII with 12mb installed, the missing 2mb comes out of the soldered RAM, not the SIMMs. When sizing memory, the onboard RAM gets temporarily relocated to 8mb, meaning the max RAM that could possibly be detected, even if the various tables are updated, is 8mb. Additionally, when the 4mb of onboard LCII RAM gets relocated to 8mb, it can no longer access the top 2mb of that RAM, which seems to me to indicate a limitation in the VISA memory controller.

 

So, given all of that, it would appear the memory controller is limited to 10mb, but even if it is not, there are several places in the ROM that limit available RAM on the LC & LCII.

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