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I touched on this subject awhile back, but now I am thinking about it and going forward with it.

The ram card was a successful failure, it worked great and I sold quite a few but interest dropped off quickly, and ebay was not getting any more interest. There are still a few I might assemble, but ultimately with little demand i scrapped the project, and will likely come to a close. My thoughts on that is probably that most portables come with at least a 1 to 3MB Ram card already which is plenty for the machine. But I digress...

So this is my next idea. Thoughts? As far as I am aware, there are no accelerators that exist for this machine. And I want to be able to run a 68020/68030+ just because I can. 

 

This is going to be a large project with many roadblocks I am sure. One being the machine isnt 32-bit clean of course, and I dont know how mode32 is going to act because I am sure the machine is going to return a gestalt that isnt like anything thats ever been seen. lol. 

 

For now, i think it will remain DelcROM-Less and simply take over the 68000 as a bus master. So without ROM, or drivers, itll appear as a 68020, and probably will not see the FPU without some sort of a patch to tell the OS that an FPU is present. 

 

This processor upgrade will probably over-tax the internal 5V regulator, but I have that covered. the full battery voltage I think is present on the PDS, so I will likely use an on-board switching buck regulator to power this card outside of the main system power. 

post-366-0-62728800-1423866434_thumb.jpg

Edited by techknight
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The biggest obstacle I see is that the cost of 68030 chips faster than 16MHz has been rising the last few years.   Although, there is a lot of ten 40MHz 68030s for $150 available at the moment.    Many others (singletons) are listed in the $30 - $50 range.

 

In any case, the supply is not reliable, but for the volumes you're likely looking at, that probably doesn't matter.

Edited by trag
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Was not one theory to upgrade the hard drive to an SD drive. This would free up power for the accelerator. In fact I think one suggestion was to run power to the card via a y-splitter for the SD drive. It would be a weird work around, but it would still be plug and play.

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Yea, theres alot of things to consider. Which is why its in the discussion/brainstorm phase. Most accelerators were designed back in the day with PAL/GAL logic, and those things were massive power hogs. 

 

Has anyone here taken temp readings off the SE/30 PAL ICs? Yea..... BTW the SE/30 logic board by itself pull around 1.75 to 1.85 Amps on the 5V Rail when its running. Yes, i know this. lol. 

 

Nowadays, its all CPLD/FPGA so it should consume alot less, but of course the processor will consume a fair bit. How much? I dont know, I will have to look at the datasheet.

 

As far as speed is concerned, it might be cheaper for me to go with a QFP package pulled from junk logic boards. 

Edited by techknight
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Well I have a possible NOS Portable mobo coming from a member here. Odds are its still dead, even if NOS. But it may finally provide a base to get a working re-cap. If she boots, I will want a memory card for sure. If an accelerator comes from this, I would love one too. I am not too concerned about processors and such. I have a bunch of spares anyway and I bet some other members have extras like me. So dont let that small point hold you back. You could probably supply then loaded or not.

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Well, theres multiple ways I can go about it. 

 

As far as clock speed is controlled, I will likely use an ICS511 which I have in the past, its a jumper-adjustable PLL clock multiplier. So I can 1.5X or 2X, or etc the base system clock which is 16Mhz

 

but also include a jumper to run at 16mhz, or use an external crystal. But I know for a fact I have to use and/nor/flipflop gates to sync up with the 16mhz clock due to the VPA/VMA/E synchro bus to talks to the SCC/VIA. 

 

I do need to figure out how DTACK is handled. I think its generated by the RAM controller instead of the GLU on the Backlit model. This is important because if I double the clock speed, that means there is going to be two wait states inserted for every single wait state on the bus, (Macintosh LC anyone?) and if DTACK comes too early then it may cause me issues with RAM accesses. Then again, since the macintosh will be treated as a 16-bit port to a 32-bit processor, its going to take two cycles for every 32-bit data transfer anyway. (again, Macintosh LC anyone?)

 

What would be awesome is if I can attach the 8MB of SRAM directly on the 030 CPU and make it 32-bit RAM instead of the 16-Bit RAM onboard. that would increase performance drastically, BUT the thing that gets in the way of this is the Overlay function. Somehow I would have to ignore the system board during RAM read/write accesses. But at the same time still follow the overlay during RESET

 

hmmmm soo many things. lol. 

Edited by techknight
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Techknight I'll buy one... :) :) I came thru on the RAM.. lol.. But I want one if you make em.... I could also give you some 030 processors for it... and co processors...  to cut your cost... I've got a strange ROM card for the portable now.. Similar to Hap's.. Says ESPIRIT Apple Confidential.. 

 

Matt

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Yeah, I understand.

 

What could be done is some sort of hybrid, where the discrete CPU is used, and an FPGA is installed with some super simple dummy code so the accelerator works as if the FPGA weren't there. This would allow you to get the basics working, and then as you learn more about programming the thing, you can use it to emulate anything else that might be wanted, such as an MMU or FPU (and any related GLU logic).

 

Or at least design the circuit with an FPGA in mind (with any necessary stuff needed to get it working electrically) so somebody (if not you) can add it later without a major redesign.

 

c

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Love it.

 

I was kind of thinking about making an accelerator board for the compact Macs, like the Plus and SE. Not that there weren't plenty of those around back in the day, but they're not exactly common now. And it would be fun to add modern goodies to it. If that interests you at all, I'd be happy to help, and I think there would be a much bigger market than for a Portable-specific accelerator. 

 

Either way, I think the only 68000-family CPU that's still in production is the 68SEC000, which goes up to 20 MHz. Digikey has the 16MHz version for about $15 if you're buying a few at once: http://www.digikey.com/product-detail/en/MC68SEC000AA16/MC68SEC000AA16-ND/954577

 

Beyond that, if you want 68K family, you'd probably have to use a Coldfire or Dragonball CPU. But I'm not sure those are still available either, and they're different enough that there might be software-level or ROM code incompatibilities.

 

Maybe you could find a box of old stock 68030's from one of the surplus parts warehouses or through octopart.com

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Well, I think there is an open core/source project for FPGAs for at least a 68020 accelerator with FPU emulation as well. inside a single FPGA. 

 

That might be an option, although a bit over my skill level. I dont mind making an accelerator or joining in for other machines as long as I can backtrack and apply it to a new PCB to support the portable. 

Edited by techknight
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Thinking about using an XC95144XL because of its high pin-count. This will allow me to route the entire address bus plus all the PDS signalling, as well as all the special control and handshake lines from the 68030 as well. 

 

This gives me room for experimentation of the logic without the need of re-spinning the board. I think these CPLDs have enough drive current to manipulate the bus directly using internal buffers. Save costs, but scouring the datasheet to be sure. 

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What functions do you need to implement inside that CPLD? 144 macrocells is not much by today's standards, but if it's purely for address decoding it should be more than enough. 

 

You might also consider using a level converter chip and a more modern 3.3V-only CPLD. The XC9500XL series is kind of old and crusty, and not the cheapest if you're worried about costs. The chips run at 3.3V but have 5V tolerant inputs (supposedly), but the 5V tolerance only applies once the supply voltage has reached some minimum level. I use the XC9572XL in the Floppy Emu, and it's the chip Uniserver has managed to fry like 10 times with his experiments. If I were doing it all over again, I'd use some kind of buffer or level converter chip, rather than connecting 5V anything directly to the CPLD. 

 

A chip like the 74LVC244 is a cheap and easy way to convert 5V incoming signals to 3.3V outgoing signals. For 3.3V to 5V, you might actually be able to drive 5V parts directly if the parts you're driving have a Vih threshold below 3.3V. Or use something like a 74LS244 to convert 3.3V to 5V.

 

One thing that's never been clear to me about accelerator design - how do you deactivate the old CPU, assuming it's not physically removed? Would you use the 68K's bus request input to gain control of the bus, then just never give it back?

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Basically the CPLD is going to be performing 3 functions, Well 4. 

 

1. Setup A0,A1,SIZ0,SIZ1 to tell the CPU that its working with 16-bit bus cycles. 

2. Handle VPA/VMA/E Sync for synchronous bus accesses. 

3. Handle decoding for the FPU, Decoding FC0/FC1/FC2 for CPU space, and decoding a couple address lines to determine that its the primary co processor, as the 68K can address multiple coprocessors. 

4. Handle bus-mastering, gaining control and turning off the primary processor. 

5. Adding propogation delay via flipflops/AND gates to fix the bus-cycle pipelining. the 68020+ is a 3 clock period bus cycle whereas the 68000 is 4. So a 1 clock cycle delay needs added to step1 for the DSACK/AS/DS. 

 

For getting control of the bus, its like this: 

 

First you toggle and hold the Bus Request line. The CPU then returns back a Bus Grant. The device that requested bus access, Then recieves the bus Grant. Once the Address/data strobes have returned to an idle state with the main CPU clearing the current bus cycle, the Bus Grant Acknowledge line is then toggled and held by the device requesting the master. it continues to hold it, along with Bus Request until its ready to give up control. 

 

When your finished, you release bus request, and bus grant acknowledged. The main CPU then looks at the bus state before releasing Bus Grant. And once its fine, the processor latches back in and takes over. 

 

So CPLD toggles bus request, waits for Bus grant. CPLD gets bus grant from CPU. CPLD then checks bus states with a decoder (make sure current cycle is complete), then CPLD latches and hold Bus Grant Acknowledge until its done with the bus. This is to prevent bus contention, to prevent the bus mastering device from taking over before the CPU is finished with the current cycle. 

 

Electronically, bus grant would be ANDed with the DSACK/UDS/LDS/AS, output of the AND would then be going into a flipflop which would latch onto the BGACK, and hold it until the flipflop is cleared. Its cleared when bus request or bus grant goes into inactive state. 

 

Inactive state happens when the accelerator gives up control to another bus master device (which the SE/portable doesnt have so not important), or the system is power cycled or reset. Multiple bus masters would need another chip on board to handle arbitration prioritization. such as a DMA controller. So if for example the SCSI controller is DMA capable, and is a bus master (add in card) and wants the bus, the arbitrator would get the request from that slot. This would cause BGACK to get released and then the SCSI takes over the bus until its finished. Then the CPU card tries to take back over when it goes inactive again. This can get complicated. 

 

But again for the portable, or any other low power 68K mac, there is no other bus mastering that I am aware of. The video generation circuit remains in question though, especially for SE as its constantly pulling from the RAM for its framebuffer, without the CPU. 

 

If you want to get really clever, you could attach the bus mastering logic to another address-decoded register. So the CPU accelerator is not doing anything, or running until you write the register via a poke. 

 

So, like sonnet, you load an extension which sees and turns on the card, card then takes over the bus and assumes control. So in a situation where you need to save battery life, or a program is unstable with the accelerator, you can turn it off via a control panel. 

 

As far as CPLDs are concerned, I want to stick with xilinx as thats who I have a programming cable for. Knock on wood, I havent blown up 1 CPLD in my RAM card project, But I did use 74 series level shifter style buffers, And, I used resistors between any CPLD lines that didnt route through the buffer. 

Edited by techknight
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I got some documents that I will have to dig up, but I have schematics of an accelerator with FPU that is discrete logic, and I have a couple sheets on an accelerator that uses PALs with PALASM. 

 

And of course there is the motorola Application Note AN944 which explains how to use a 68020 in a 68000 system. it was located and posted in my RAM thread. 

 

There is also a working accelerator out there that uses a large scale FPGA with 68K softcore

Edited by techknight
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Take a peek here:

 

http://microprocessor68000.tripod.com/

 

Under bus arbitration it gives a good explanation. 

 

Also, I attached my library of documents I have. Just with these alone, an accelerator could be built inside a CPLD and real CPU easily.

 

Oh, if you do jump into making one for an SE, might be worth it to toss a SONIC chip on there and get ethernet too! ;) and maybe even address selection for flash ROM to do netbooting. haha. now I am getting carried away. 

 

PAK68 Accelerator Schematics - c't 1987.pdf

AN944.pdf

LUCAS-11.pdf

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Oh, if you do jump into making one for an SE, might be worth it to toss a SONIC chip on there and get ethernet too! ;) and maybe even address selection for flash ROM to do netbooting. haha. now I am getting carried away. 

 

<in quiet voice>  and add a micro to USB chip at some unused memory space and wait for someone to write drivers for it...

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<in quiet voice>  and add a micro to USB chip at some unused memory space and wait for someone to write drivers for it...

Yes! And add WiFi while you're at it!

 

And how about SATA? SATA I is fine, since these Macs (especially the SE/Portable) will never come even close to maxing it out.

 

c

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