Jump to content

tattar8

6502
  • Content Count

    191
  • Joined

  • Last visited

Everything posted by tattar8

  1. This is amazing. Are you planning to make the gerbers for the accelerator available like you did the cache card? Edit: didn't realize this thread was 2 months old.
  2. It's part of the ratcheting mechanism that spins a gear on the toner. It's broken into 5 pieces on mine, but I glued it back together to see what it's supposed to look like; it's still not nearly strong enough to actually be used. Anyone know where I can find a replacement, or does anyone have an stl file for it?
  3. I have a IIci board which apparently had a dead 68030, which was removed leaving a clean pad. I'm trying to figure out what I can use to replace it. I know the IIci ran at 25 MHz, but for some reason 25 MHz 68030s are expensive on eBay. However, 33 MHz chips seem to be far more plentiful. Will a 33 MHz chip run fine at 25 MHz in the IIci? This is the part I'm thinking of using: https://www.ebay.com/itm/1pcs-MC68030FE33C-ENHANCED-32-BIT-MICROPROCESSOR/392523139565
  4. Sounds like everything needs a recap.
  5. I did the initial lubrication before seeing that video, and did it the same way as I've done others, following the guide here: https://wiki.68kmla.org/Floppy_drive_lubrication, where the instructions are to use white lithium grease, which is what I used. It seems like it slides easily. The four press-fit washers you're talking about are the ones closer to the center of the floppy tray, right? How do you get them out?
  6. The new gear has arrived, I installed it and lubricated the gearbox, and put it all back together. But the eject mechanism is still not able to fully engage -- the motor spins and pushes the cage up halfway, but not enough to actually eject the disk. I've already also lubricated the mechanism, and it doesn't feel any harder to do it manually than other drives. Any ideas?
  7. Update: I opened one of the first two's eject mechanism gear box, removed the gears, and found that it was just stuck, even though the grease wasn't that bad. I re-greased it and put it back together and now it's good as new. I also lubricated the third one's drive tray, and cleaned it with IPA, so now it's able to accept a disk properly, but any disk I insert immediately results in an unreadable disk message within a second (so too fast for it to actually have read the disk). It also couldn't eject similar to the other two. I opened up the gear box and found that
  8. I wasn't sure where to post this as this spans Mac categories (these drives came from a II-series, Portable, and SE/30). I have 3 drives that are dead and am wondering if any of them are likely to be fixable, or if I should just toss them and not spend hours on a futile effort. Two of them exhibit the same symptoms -- they seem to work (but need a head cleaning), but will not eject. I would suspect the infamous eject gear, but I don't hear any indication that the eject motor is even spinning. Is this some simple fix, like a capacitor that needs replacement or somethin
  9. The Mac now boots. Swapped all the capacitors and she fired right up. This machine came with a Supermac video card (looks like a Spectrum/8 Series III), but I had to swap in a Mac II video card since the Supermac was having trouble with the monitor I'm using. The hard drive (looks like an aftermarket Quantum) is totally dead, which is no surprise, but I have a spare SCSI2SD to throw into it. The bigger issue is the floppy drive, which seems to be in bad shape. It needs to be cleaned and lubricated, which I can do, but what I'm not sure about is the fact that it makes a constant
  10. I’ll check to see if there was over voltage on the 12v line; I should be able to power on the supply without the logic board if I just provide +5V from USB or something, right? These were the factory tantalums, so they shouldn’t be under specced.
  11. In that case I'll wait; the caps will probably show up this week, so I don't save a lot of time by trying to boot the machine now. I did desolder C1 (far more easily than I expected) and found that the pads underneath were pristine. Could it be because C1 is the only one on the 12V rail? All the others are on 5V I believe.
  12. I recently acquired a IIfx that was sold as totally dead. When it arrived, first thing I did was remove the old batteries and swap in new ones (since this machine won't power on without them). I then tried to turn it on. Clearly the batteries were the cause of the "totally dead" issue, since it immediately powered on. However, within seconds (so don't know if it chimed yet) C1 exploded with a bright flash and released its magic smoke; this board was already populated with tantalums. I immediately yanked the power cord and shut the machine off. According to the schematics, C1 i
  13. There's an entire archive of A/UX software that gets installed under /usr/local kicking around somewhere. It includes a bunch of GNU tools including GCC. I just FTPd it to the box and untarred it there. It's here: ftp://ftp.atlas.altexxa.net/software/mac/unix/robbraun/aux-usr.local-10172010.tar.bz2
  14. When you say it's behaving weird, what exactly does that mean? You get signs of life out of it but it behaves erratically? If you even get a chime (either kind) out of it I'd think that eliminates the CPU as being the problem. I have a IIci with what I believe to be a dead 68030, and that's because it does nothing at all after poweron -- no chime, nothing on the address lines, etc, even with a good system clock.
  15. Yes, that notch is there to mark Pin 1.
  16. That software can read old unknown ROMs? Last time I tried I wasn't able to make it work either, trying to read a ROM out of some old 6502-based terminal I was messing with. For that thing I ended up just wiring up a microcontroller I had laying around.
  17. On my board, the 74LS253 was installed on a little PCB attached to a header. I just removed it and used a jumper to jump the two pins that corresponded to the cut trace. Now as far as the Mac is concerned, it's back to only having 128k.
  18. Do you know of any ready-made development boards for Atmel/Microchip's CPLD lines? I can't find any, and I really don't want to spin my own board for one at this point. I built a circuit based on the VHDL code that generated the waveform I posted earlier, but while it didn't stop the machine from booting normally, it still didn't allow larger RAM sizes. @Bolle Did I completely overcomplicate this? Does the GAL's logic for the WE not worry about CAS-before-RAS at all, and instead just holds WE high whenever RAS is high regardless of what CAS is doing? So this whole t
  19. Nice! So you downgraded the 512k back down to 128k? I just got my hands on a 128k that has also been upgraded, and trying to figure out what I need to do to reverse the upgrade. What did you have to do?
  20. The Mac II has separate CAS and RAS lines going to each SIMM. Does that mean that all the banks are getting refreshed independently? Or can I assume that while accesses may occur at different times, the CAS-before-RAS refresh will always be synchronized? If they're completely independent, then I'll need to build the whole design 4 times, which would make it impractical to just use 74 series logic, and instead actually find a CPLD or FPGA and appropriate level shifting hardware (since all the ones I can find run at 3.3v).
  21. Could I just throw a series of noninverting buffers on the /weout to introduce some propagation delay?
  22. I threw together some VHDL to simulate the circuit design. Does this behavior look correct?
  23. So if I understand this right, during a CAS-before-RAS refresh cycle I want to keep WE high for some brief period after RAS drops low. So I need to determine whether or not such a cycle is occurring, and then hold WE high. Am I right in stating that the CAS-before-RAS cycle is the only time at which CAS will drop while RAS is still high? If so, I could just use a D latch on the CAS and RAS signals (~CAS to the E signal, and RAS to D), and a 3-input AND gate (Q, ~CAS, and RAS) (please tell me if I've made a mistake, digital logic design is not my strong suite).
  24. So is it possible that UH7 on the SE/30 doing the same thing as the PALs on these SIMMs?
  25. So the crucial bit is only the section governing /o19? That seems like it could be implemented by a couple of 74 series chips on a breadboard. Looking at the Bomarc schematics for the II, which shares the same RAM system, each bank's /W is controlled by G7, a 74F240 inverting buffer. But both outputs are being fed the same input, and are controlled by the same OE signal, so are they really just the same signal? If so then I can just intercept the /W signal at pin 17 and mess with it, then send it back.
×
×
  • Create New...