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  1. I think Rene Vega claimed that the Mac OS 8.6 and later MP nanokernel once supported it.
  2. Yes, System 7.5 is what introduced PC Exchange.
  3. They are generally contiguous on pre-IIci machines. I believe that the IIci always dedicate 64MB to bank A and use the PMMU to remap.
  4. It would be easy to support both with the same ROM code, and I believe that the ROMs are exactly the same.
  5. This also reminds me of the difference between 350mil vs 300mil 4Mbit chips.
  6. That is not how DRAM generally works. In fact, I think 80ns was the most common DRAM when the Mac Classic was new. And yes it is possible that the 1Mbit DRAM chips on the daughterboard itself may be bad.
  7. Notice they have a PAL on them. I wonder what asymmetric DRAM addressing do they exactly use.
  8. Actually, the absolute minimum RAM limit for System 7 to boot is 1.5MB.
  9. The reason why it is 200ns BTW was that Apple was one of the early adopters of 256k DRAM back when the chips was expensive. By the time the 256k DRAM chips became more common, it was already mostly replaced by 150ns.
  10. More precisely, it was the early Micron DRAM chips that had problems. Of course, eventually they improved the quality of the chips around the time many other US DRAM manufacturers was forced to shut down after DRAM prices fell in 1985.
  11. Yea, I think the early Micron DRAM chips had a high failure rate.
  12. They also used MT1259 for 256kx1 later on for example.
  13. Yes, the chips on 16MB 30-pin SIMMs are supposed to be 16Mx1. To use 4Mx4 chips would require extra logic. These SIMMs was never very popular for several reasons (including early 16Mbit chips being expensive and 400mil). I wonder which kinds of addressing the 512KB/2MB/8MB SIMMs with PALs uses.
  14. Really? It is true it sometimes reconfigures the memory controller, but...
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