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Please help me figure out what the deal is with this IIx RAM

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micron produced actually 1Mx4 DRAM ICs without JEDEC testmode implemented.

like mt4c4005 and "newer" produced DRAM also dont have the jedec testmode in the datasheet

also found a detail description about the  difference in the datasheet, maybe it help

 

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Edited by chiaki

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Following the SE/30 schematics it should be possible to implement the same simple logic into the Mac II logicboard.

The independent RAS lines going to the SIMMs originate from the same two RAS signals coming out of the GLU gate array just like the SE/30.

 

Everything that should need to be done on the Mac II is grabbing those signals somewhere from the logicboard and feed them into a GAL:

 

-R/W - UG7 17/GLU 52/

-RAS.A - GLU 78/UH14 2&4

-RAS.B - GLU 79/UH14 6&8

-CAS.LL - GLU 80/UH14 11 (original) or 5 (buffered) (all the CAS signals should be the same, otherwise the SE/30 approach would not work and it's using the same GLU gate array)

 

Then we remove R19 and R23 on the back of the logicboard to cut the traces between the buffer UG7 and the /WE pins on the SIMM sockets.

We will have to inject our new /WE signal either into two vias next to the battery or next to UG7 where the two resistors have been before.

 

In the GAL we just make sure /WE to the SIMMs only gets activated when the accompanying RAS signal is active and keep it latched as long as RAS is there, no matter what R/W is doing from then on.

 

This hack is completely reversible, just remove the wires you tapped into places and solder the two resistors back on.

I am going to try this on a Mac II logicboard I just got after I finish recapping it and will report back.

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Dumb question... if the II and IIx are in part slow because they were designed for 120ns RAM and have a large number of wait cycles... if you have faster RAM is it possible to change the number of wait cycles in the ROM, for example with a ROMinator?

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