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Bolle

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    2012
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    Germany - Bavaria

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  1. I made a two layer version out of the schematics that fly around on the interwebs because cheap: Couldn't get them to work reliably yet because of the whole PCB thickness thing. If you wiggle them around before use and put on rubber bands they are ok for a while. What thickness did you choose for yours? I ordered some in 1.6mm as well as 1.2mm from JLCPCB. 1.6mm is really tough to get into the socket and 1.2mm is more on the floppy side of things. IIfxRAM_2Layer.brd IIfxRAM_2Layer.sch
  2. Bolle

    OrangePC Ram problem

    The 386 has a 16bit data path. A 30pin SIMM is 8bits, so you'll need at least two matching SIMMs installed at a time. Not sure on Windows 3.1 and actual RAM usage.
  3. Bolle

    OrangePC Ram problem

    386s do not support more than 16MB extended memory. In fact I couldn't even get my card to work with anything but 4*1MB SIMMs yet.
  4. Bolle

    Macintosh portable clutch mechanism

    Made the same mistake but instantly realized that it could be a bad idea because the clutch might contain some sort of springs inside. Looked it up, saw what happen to @BadGoldEagle and ripped mine open to dry them out again. I then proceeded to remove the springs that were inside, cleaned everything, put in silicone based grease and put everything together again. Clutches are butter smooth again now. I guess I dodged a bullet there.
  5. Gerbers attached. BOM -C1-C11: 0.1uF 1206 ceramic caps -C12, C13: 22uF/10V tantalum or electrolyte caps -R1: 330Ohm -R2, R3: 220Ohm ->pad size is metric 1206 for all the above resistors and caps -U5-U8: 32K x 8 SRAM 15ns SOJ (IS61C256AL-15JL, IDT71256SA15 and the like) -U9, U10: 8K x 8 TAG SRAM 12ns SOJ (ATT7C174J-12, IDT71D74S12... only exists as NOS, no modern replacement) -U1: GAL20V8 10ns (7ns works as well) PLCC28 -U2, U3: GAL20V8 7ns PLCC28 -U11: 74F74 SO14 -U12: 74F125 SO14 -J1: 1.27mm pitch 2 x 50 SMD pin headers cachecard.zip
  6. Looking good... On one of my Carreras the cloned cache card would not be stable with 40MHz. Everything is fine at 33MHz though. After some back and forth it turned out that not all combinations of CPU and cachecard will run at 40MHz. I swapped around different CPUs and even found a combination where the original cachecard would refuse to work resulting in a hard crash once the Carrera INIT loads. I will be revising the PCB design a little and then post the gerbers and a BOM so everyone can build their own cachecards.
  7. Bolle

    LCIII battery 'splosion

    Carefully file down the chip package to expose the internal trace where the leg did break. You can solder a new leg to that trace if it didn’t corrode internally. I will have to look at the schematics but you might get away with a 42 pin EPROM like a 27C160 as a replacement.
  8. Bolle

    Bolles finds

    I will document what I am doing with this machine along the way. And gather information that others already documented elsewhere already, I know techknight somewhere gave an excellent explanation on the workings of the power circuit and what happens when the machine is powered in one of the countless wrong ways. But thanks for the heads up nevertheless. Those machines are finicky beasts.
  9. Bolle

    Bolles finds

    You can run a Portable that way when it’s done the right way. My plan was to wire my plug on the back right to the power connector on the logicboard. That will replace all the battery switch wiring that can fail and will make bad things happen. So it’s actually safer to do it that way if you ask me.
  10. Bolle

    Bolles finds

    Picked up one of those beauties today: All the plastics are intact, it has a battery installed that has already been cut open but looks like it's still holding the original cells, no obvious leakage from either the main battery or the 9V block. It looks more yellowed in the pictures than it actually is. Sitting next to my other Macs it really shines in bright white compared to most of them. It came without a charger and no HDD installed. I will have to free some time to disassemble the whole thing, clean all the plastic parts and inspect the logicboard. It will obviously need new caps if it hasn't been recapped yet. My plan is to install a plug on the back at the little expansion cover, connect that to the main battery plug on the logicboard and power it that way from a lab powersupply to get around having to recell the battery. Not that anyone's actually carrying around anyways Making one of those HDD cables is on the list as well as maybe getting one of the RAM cards that are going to be made. (maybe, because the available video card clone also looks tempting but that's likely going to conflict with more than 4MB RAM)
  11. Bolle

    Schematic for the IIe Card?

    I think those are actually 22uF instead of 220uF. It probably would have worked just fine even without the cap that fell off. I think both caps are just connected between ground and 5V.
  12. Bolle

    Well Crap (SE/30)

    Leave the diodes and the crystal out for now and see if you can get the board to boot at all at first before spending money on parts. Those parts are not critical for the board to work. Without the diodes you won't be able to use a battery and without the crystal the clock will not advance in time.
  13. Looks good, but you want to make sure that the time between /ras going low and /weout going low is greater than the test mode setup hold time of the chips on your SIMMs. With a modern CPLD or FPGA this is an easy thing to implement in the logic. With a GAL or discrete logic you will have to use chips that have long enough propagation delays.
  14. Sounds perfectly correct. I have got another set of SIMMs from the same manufacturer and they do have a GAL as well but do not work in the Mac II. I will compare those to the ones that work someday soon. If I get lucky and the wiring on the SIMM has separate /RAS, /CAS and /W signals to the chips those could be made to work as well.
  15. That should work. You will need the /RAS signal as well and make sure that your logic chip is slow enough to exceed the hold time for the test mode. So you would have to make sure what type of RAM you are using beforehand to meet the timing requirements. The only thing that you want to make sure is that /W does not become low while you are in the setup or hold interval for the test mode of your RAM chips which depends on when /RAS is going low. Take a look at the datasheet for any 4M DRAM chip and the timing diagrams will make it obvious what you need to do.
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