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  1. tattar8

    Corroded Chip

    When you say it's behaving weird, what exactly does that mean? You get signs of life out of it but it behaves erratically? If you even get a chime (either kind) out of it I'd think that eliminates the CPU as being the problem. I have a IIci with what I believe to be a dead 68030, and that's because it does nothing at all after poweron -- no chime, nothing on the address lines, etc, even with a good system clock.
  2. tattar8

    Corroded Chip

    Yes, that notch is there to mark Pin 1.
  3. tattar8

    LCIII battery 'splosion

    That software can read old unknown ROMs? Last time I tried I wasn't able to make it work either, trying to read a ROM out of some old 6502-based terminal I was messing with. For that thing I ended up just wiring up a microcontroller I had laying around.
  4. tattar8

    Macintosh 128k replacement went (almost) perfectly!

    On my board, the 74LS253 was installed on a little PCB attached to a header. I just removed it and used a jumper to jump the two pins that corresponded to the cut trace. Now as far as the Mac is concerned, it's back to only having 128k.
  5. Do you know of any ready-made development boards for Atmel/Microchip's CPLD lines? I can't find any, and I really don't want to spin my own board for one at this point. I built a circuit based on the VHDL code that generated the waveform I posted earlier, but while it didn't stop the machine from booting normally, it still didn't allow larger RAM sizes. @Bolle Did I completely overcomplicate this? Does the GAL's logic for the WE not worry about CAS-before-RAS at all, and instead just holds WE high whenever RAS is high regardless of what CAS is doing? So this whole thing boils down to simply "RAS * WE", which I can just build using a single AND gate?
  6. tattar8

    Macintosh 128k replacement went (almost) perfectly!

    Nice! So you downgraded the 512k back down to 128k? I just got my hands on a 128k that has also been upgraded, and trying to figure out what I need to do to reverse the upgrade. What did you have to do?
  7. The Mac II has separate CAS and RAS lines going to each SIMM. Does that mean that all the banks are getting refreshed independently? Or can I assume that while accesses may occur at different times, the CAS-before-RAS refresh will always be synchronized? If they're completely independent, then I'll need to build the whole design 4 times, which would make it impractical to just use 74 series logic, and instead actually find a CPLD or FPGA and appropriate level shifting hardware (since all the ones I can find run at 3.3v).
  8. Could I just throw a series of noninverting buffers on the /weout to introduce some propagation delay?
  9. I threw together some VHDL to simulate the circuit design. Does this behavior look correct?
  10. So if I understand this right, during a CAS-before-RAS refresh cycle I want to keep WE high for some brief period after RAS drops low. So I need to determine whether or not such a cycle is occurring, and then hold WE high. Am I right in stating that the CAS-before-RAS cycle is the only time at which CAS will drop while RAS is still high? If so, I could just use a D latch on the CAS and RAS signals (~CAS to the E signal, and RAS to D), and a 3-input AND gate (Q, ~CAS, and RAS) (please tell me if I've made a mistake, digital logic design is not my strong suite).
  11. So is it possible that UH7 on the SE/30 doing the same thing as the PALs on these SIMMs?
  12. So the crucial bit is only the section governing /o19? That seems like it could be implemented by a couple of 74 series chips on a breadboard. Looking at the Bomarc schematics for the II, which shares the same RAM system, each bank's /W is controlled by G7, a 74F240 inverting buffer. But both outputs are being fed the same input, and are controlled by the same OE signal, so are they really just the same signal? If so then I can just intercept the /W signal at pin 17 and mess with it, then send it back.
  13. Nice, this might be helpful. How did you generate that code from the GAL?
  14. Theoretically, would it be possible to design a board that hooked straight to the address and data lines (perhaps by hijacking the FPU or ROM socket) and had all the memory muxing and refresh logic onboard, allowing use of any standard SIMMs, essentially bypassing the ones on the board?
  15. tattar8

    What's wrong with my SE/30?

    The odd thing was it was working consistently with a MacSIMM, but after I swapped it out for a ROMinator II, neither worked consistently anymore. The only other problem I can think of is that the slot on the motherboard is damaged and does not hold SIMMs, forcing me to either use the rubber band method or hot glue to hold any SIMM in place. How hard is it to replace the slot?