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trag

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    Austin, TX
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    Model & Amateur Rocketry

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  1. trag

    G3 Chip Compatibility

    There have been a number of discussions, in detail, on this very point. Basically, the early PPC750's which have pins to support external L2 cache are all pin compatible. They may require different voltages, or configurations on some signal pins (PLL configuration pins, e.g.) but the balls are in teh same place. The PPC740 is different, because it does not have the capability of supporting an L2 cache, so those pins are not present and all the pins are rearranged. The 750CX adds a 256K on-board L2 cache, and so again, the external connections to control the L2 cache are omitted so the pinout changes. However, the 750CX is also not compatible with the 740 pin arrangement, although it seems like it could have been. Perhaps they're in different size packages, I don't remember. They are enough years apart, the process technology for the die could have changed and so the package size may be different as well. The 750FX and 750GX are compatible with each other, but are a change from the 750CX for some reason. So, for example, if you have a PPC750 with external L2 cache support and want to replace it with a later model that moved the L2 cache on chip, it will not be an easy task because the pin/ball arrangement changed.
  2. The boards need to be 1.27mm thick. The original spec. is for .050", which is 1.27mm. There's some +/- in that spec, but really not enough to go to 1.2 or up to 1.6. 1.6mm is .063" thick board, which is far thicker than .050". I'm amazed that you could get it into the socket at all. I posted some datasheets for SIMM sockets in an old thread, which included the specs for boards that fit into the sockets.
  3. AFAIK, the only Quadras that could go over 136 were the Q605 variants and the Q63X version that had two SIMM sockets (636?). The C/Q 610/650/800 all have, as shipped, limits of 136 MB. As it turned, as mentioned in my previous post, that was a limitation of the firmware and how memory was detected at boot time, not a limit of the memory controller hardware. Apparently, the firmware didn't check the higher Row (or column?) address lines that are needed when larger capacity memory is installed. Let's see, a 16MB bank in 72 pin memory is 4M addresses X 32 bits (4 bytes). 4M addresses is represented in 22 bits. A 64MB bank in 72 pin memory is 16M addresses X 32 bits (4 bytes). 16M addresses is represented in 24 bits. The address is "multiplexed" (split up) as ROW and Column addresses. The 30 pin and the 72 pin SIMMs support a maximum of 12 address pins/signals. So, as you can see, 16M addresses is the maximum possible (12 + 12 = 24 bits => 16M addresses), and a single bank of memory, which is 4 bytes wide, cannot be larger than 64MB (16M X 4bytes). Anyway, a 16M bank can be 10 X 12, 11 X 11 or 12 X 10, in theory. A 64 MB bank must be 12 X 12. The Quadras were seeing 64MB SIMMs as 16MB, because they were ignoring a couple of the address bits.
  4. Actually, the Quadra 610 and 650 did have a pretty hard 136 MB limit on RAM, even when larger modules were installed, until bbraun (or was it Doug, darn, now it's been too long) dug into the firmware a bit and changed some boot parameters so that the memory controller was allowed to "see" more memory. There was a thread on it around here before the system change. I hope its still around. IIRC, he took the 650/800 up to 512MB or thereabouts. Part of that may have been forced into a RAM Disk. On the SE/30, each bank of four 30 pin SIMMs is the equivalent of one, single bank, 72 pin SIMM. If you built the machine with two 72 pin SIMM sockets, they'd be limited to 16MB or 64MB SIMMs. 32 MB 72 pin SIMMs are not going to work in such an adaptation, because almost all the 32 MB SIMMs in existence are 2 bank SIMMs. They're made out of two separate banks of 16 MB. Banks are controlled by having independently controlled RAS lines. There's no reason to believe that the there are any more than two sets of RAS lines in SE/30. One possibility would be to modify the board for a single 72 pin socket. Combine the signals for the two SE/30 memory banks onto a single 72 pin Socket, which would support one or two banks. That way, one could install a single 16, 32, 64 or 128 MB SIMM and it would work. If you go with two sockets, then the only way to get 128MB would be with two separate 64MB SIMMs and again, 32 MB SIMMs would not work, or would only be seen as 16 MB.
  5. trag

    Re-capping IIsi problems....

    Take a dental pick and gently probe the solder vias (holes that go through the board, with no component legs in them). These carry signal from one layer of the board to another. They are also low laying areas where cap goo tends to pool and have an intensified corrosive effect. When I recapped my IIci back in the mid-90s, one of my vias looked fine, but was actually corroded through ("solder" was soft, rather than hard). I had to run a bypass wire to run the signal around the corroded via. Fortunately, the connected traces were on the top and bottom layers and not on an inner layer.
  6. https://www.connectorpeople.com/Connector/TYCO-AMP-TE_CONNECTIVITY/8/822019-2
  7. IIfx SIMMs are also .050" thick, and so will have the same issues seen elsewhere if one settles fro 1.2mm thick boards.
  8. trag

    Well Crap (SE/30)

    Rust-oleum sells a phosporic acid product which is great at removing rust. The phosphate displaces the oxide on iron and forms a tough coating of iron phosphate which has a black/grey color, doesn't flake off and takes paint well. However, I wouldn't recommend it if you're planning to electroplate with, e.g., chrome afterwards. I don't know if it is conductive, and other metal might not plate onto it well. It is fantastic if you just want a durable, corrosion resistant surface or if you want to paint over it. "Rust Dissolver" https://www.autozone.com/miscellaneous-cleaners-and-degreasers/rust-remover/rust-oleum-rust-dissolver-1-quart/
  9. Are the old pins still in the holes? If not, I usually do this for stubborn through-holes. 1) Grow a third and fourth arm. 2) Stand the board on edge, so you have access to both sides of the problem hole. 3) Apply heat via soldering pencil to one side of hole (liberal flux helps with good heat conduction). 4) Touch the sharp end of a sewing pin with a plastic head (plastic head provides insulation, or use regular pin with gripping tool) to the other side of the hole. 5) As the solder melts, gently push the pin through the hole, moving the soldering pencil from directly over the hole to the side, touching the solder pad and pin. 6) Withdraw the heat. 7) Withdraw the pin. The timing between steps 6 and 7 can be a little tricky. I usually find that solder doesn't stick to a stainless pin, so one is left with a little volcano of solder sticking up on the heat side. But, if you're too late, the solder may manage to harden and grip the pin. If you're too early the solder may just flow back into the hole after the pin. But the timing isn't super critical. This rarely gave me trouble. Maybe one time in 20 or so. If the pins/socket are still in the holes, I usually do the following -- however, note that I've only ever done this on PCI cards, to remove DIP chips, not on an SE/30 logic board, so YMMV: 1) Support the board with the connector/chip facing downward and room for the connector/chip to fall out of the board. 2) cover any nearby components in modeling clay so they won't blow away. 3) Apply heat from an adjustable heat gun (has a ~2" wide nozzle) to the solder holes with one hand. 4) With the other hand, probe the solder in the solder holes with a dental pick, while heating. 5) Move the heat gun as needed to melt any holes that are still hard. 6) Gently push the connector/chip off the board by pushing the pins down out of the holes once the solder is melted in all the holes. Again, liberal flux is helpful for this method. Finally, another possibility is to use a product called Chip Quik. It is an alloy which mixes with solder and lowers its melting point. I used to use it a lot, but eventually got to where I don't really need it, but ti can be a life saver for those difficult situations. My main complaint about it is that you really need to clean it all up off of your work, when you're done and that's tedious. No doubt others will be along with other advice. There's lots of ways to skin the soldering/desoldering cat.
  10. trag

    mattsoft's IIfx

    Nice. No real comments, but want to encourage you to keep posting progress reports. I am enjoying reading about it.
  11. Ah, here we go. Perhaps this friend could be asked? BTW, did you friend get info on how the cache size/speed is encode on the Flash on the board? I ask because i have some G3/512K Cache upgrades and I am sorely tempted to replace the SRAM chips to take them to 1MB, but there's no point if it won't be recognized.
  12. That's a good idea -- for someone else to do. Didn't you mention that someone else had had success? Perhaps that person could be contacted. Presumably, he has established a friendly beach head at Sonnet?
  13. Is there any potential use for the other 2MB? I think there are some 256K X 36 @ 250 chips in the $4 - $6 range, so it would probably make more sense to use those. I'm not certain, as I browsed scores of SRAM chips and the brain is full. It all started with a simple search for some Galvantech chips on a Sonnet G3 card, which popped up a link to Digikey where they were clearing them out for $1.7X (don't remember 'x'). 128K X 36 @ 250. And I just kept looking. It looks like Cypress passed a lot of their old product on to Renessas (sp?) or discontinued a bunch of the old line of SRAM chips recently and there's a bit of a fire sale going on.
  14. Atmel and Altera still have 5V CPLD lines available. Atmel was bought by Microchip. https://www.microchip.com/design-centers/fpgas-and-plds/splds-cplds
  15. Just posting a couple of files. One is the Motorola/Freescale ZIF datasheet which was linked to earlier. The link is not working. The other is an IBM doc on connecting/configuring L2 cache chips -- but it's only for the 750/G3, not for the G4. MPCPCMEC.pdf 750_dg.pdf What is the maximum size for the G4 L3 cache? I ask, because Digikey has some Cypress chips on clearance (no warranty/no returns) which are 250MHz, 512K X 36, $9.10 each. So a pair of them would yield a 4MB L3.
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