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IIsi PowerCache TwinSlot Adapter - Cloning Project

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Noticed something strange about what appear to be connections between the FPU pads and the GAL(?) adapter IC on this board. Since there's an SE/30 Adapter Cloning Project, a dedicated  thread concerning this facet of the overall PowerCache Adapter Cloning Project seems in order. Lines of research are beginning to get muddled. ::)

 

post-902-0-97963600-1484239555_thumb.jpg

 

This PCB is a humdinger! There are traces visible on subsurface layers on both sides of this four(?) layer board.

 

 

 

 

 

 

edit: any help in buzzing connections on this card would be a significant contribution and greatly appreciated.

Edited by Trash80toHP_Mini

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The FPU pins in question seem to be CS and RW on the bottom side, A1 and A4 on the left, and top seems to be SENSE, D0, and D3. I suspect there's more hidden through vias. It seems that the GAL may be handling the decode/select function for the 68882 coprocessor interface, as blatantly evidenced by the fact it has something connected to the 882's CS input.

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I was thinking along the lines of the FPU just hanging out on the system bus and the GAL monitoring some signals from its pads in order to tweak the address space of the IIci Slot adaptation. Dunno, maybe some help will be offered tin clearing a few things up.

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It could be doing both. I question why it's actually running some of those lines to FPU pads. That may have just been a case of something making the design easier by preferring to connect to the system bus via FPU pads instead of trying to reach over to the bus/connector area. 

 

d4GW7SD.png

 

This is what I was referring to with the decode/select part, straight from the 68882 datasheet. This is the precise method in which the 68882 would be connected on an IIsi PDS slot, with the "chip select code" block probably being part of the GAL. 

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Dunno, I'm all but sure the GAL has nothing to do whatsoever with the operation of the FPU. Just about every IIsi card has a socket for a 68882, even the passive right angle adapters SuperMac made for their VidCards for the IIsi. uniserver lopped off the whole FPU section of one of those cards to use it as a riser for installing the RCPII/IIsi in the SE/30!

 

IMO, any signal going into or out of that GAL is for the singular purpose of IIsi Cache Slot adaptation. Nothing else makes a lick of sense to me. The PCB designers had at least four layers to keep the PDS->IIci Cache Slot->PDS Expansion Connector bus as short and sweet as possible. That's why I was so curious about that apparent FPU connection when I first saw it.

 

Found another pic a while back that shows connections hidden in the main template pic by the IC.

 

post-902-0-34417600-1484275544.jpg

 

If anyone has the TwinSlot card, please post an assortment pictures like this taken from all around the IC and that will help a lot to clarify where some of the connections are made.

 

If you've got a continuity tester to use  .  .  .  well  .  .  .  just begging. :D

Edited by Trash80toHP_Mini

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No, the GAL absolutely has something to do with the FPU. Read back what I said about the FPU's CS input. That's the signal that tells the FPU that the data on the bus is currently intended for it. This signal is not provided on the PDS connector, and as such, must be synthesized using glue logic from the function code and address lines from the bus by the GAL, in accordance with the diagram I linked from the 68882 datasheet. If the GAL did not do this, the FPU would never work. 

 

The reason I'm pointing this out is that I was talking about how these kinds of things require you to look at the big picture, particularly with reversing the GAL. Since we now know that the GAL has to synthesize the FPU chip select signal, that means we essentially know the function of one of the outputs, and reasons why certain inputs would be used. This reduces the amount of reverse-engineering because we now know a portion of what the GAL does already. This reduces the number of possibilities to analyze from a truth table of all inputs and outputs because certain combinations are now already accounted for without even having to really analyze the circuit.

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Nope, can't see it that way at all. Look at it from this angle:

 

No other IIsi card but the PowerCache adapter has a GAL or anything like it that I've seen. I'm absolutely certain there's no active IC on the SuperMac riser card and it has an FPU socket on board. It wouldn't be on there if the FPU couldn't work from just the IIsi PDS signals. So I don't see how the GAL would be connected to that FPU pad unless it needed that particular input to do its black magic in synthesizing the IIci Cache Slot's addressing/whatever.

 

The GAL is using that signal as an input.  :)

 

 

edit: actually, I'm really tired and this could just be foolishness, I haven't determined which trace goes where from FPU to GAL or just passes by underneath it as yet. The traces stop just short of the GAL in my diagram (that's not clear in the exported jpeg) because I can't see where they go! So I'm not going to worry about it until I can try to work that new pic's info into the Illustrator file. Then more pads will appear as connections are determined from the additional data.

Edited by Trash80toHP_Mini

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Spent a little time updating the layout of the board as best I can without someone contributing by taking pictures of the GAL IC from all sides to clarify more connections. So far I've identified a few inputs and one output to the adapted cache slot for the PowerCache. HELP! :ph34r:

post-902-0-42083500-1484658289_thumb.jpg

Oh yeah! Buzzing the connections would be invaluable.

Edited by Trash80toHP_Mini

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Mirrired to match up with Solder side

 

post-902-0-82107900-1485896576_thumb.jpg

 

DiiMo card also mirrored. No Solder Side pic available as yet: DiiMO-SE30_Dual_Slot-10.jpg  .  .  .

 

post-902-0-51368200-1485896831_thumb.jpg

 

ARTMIX Clone detail as compared to DiiMo Adapter: ARTMIX-DIIMO_GALs-Detail-20.jpg

 

post-902-0-61793700-1485896969_thumb.jpg

 

MicroMac version of DayStar TwinSlot Adapter/IIsi

 

post-902-0-84532500-1485897321_thumb.jpg

 

Mystery SE/30 Adapter for SE/30: Got info to contribute?

 

post-902-0-94350600-1485897404_thumb.jpg

 

________________________________________________________________________

 

End game for project: One card adaptable to IIsi and SE/30 with these capabilities a/o Two NuBus slots in lieu of IIci Cache slot in IIsi (possibly two Nubus Slots for SE/30 in addition to IIci Cache Slot adaptation fot Universal PowerCache Accelerator.)for my Rocket 33 and Futura II FX/Video/10bT combo card. Dunno final specs are in flux.

 

Daystar IIsi Adapter with PowerCache Slot, FPU and a NUBus slot! [:)]]'>

 

post-902-0-92719400-1485897653_thumb.jpg

 

All cards (except Mystery Card appear to this idiot to be variations on DayStar's TwinSlot Adapter for the IIsi with variations on the Adaptations by four different designers.

 

Playtime big time! [:D]]'>

 

General Purpose PDS Prototyping Card for SE/30/IIsi, gotta be an open source project for some four layer PCB design Guru's input. One 74LS input limit electrical signal limitations require line drivers for signals to be added. Auxiliary PSU input required as well as airflow enhancement to meet/exceed existing power/cooling budgets of both target machines.

 

It's all been done, just gotta figure out how and tweak with SMT equivalents to the 74LS components of the day.

 

post-902-0-86851200-1485899575_thumb.jpg

 

68030 thruholes replace FPU socket provosion on 6030PDSGPPB for jumper wiring full signal set to SMT pads for 20pin/28pin GAL Activ Adaptation for two target machines. Addition of pin level 68030 PDS Socket provides for convenient form factor Slot interface to piFrastructure/shield level hacking.

Edited by Trash80toHP_Mini

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Okay, so please don't hit me if I'm wrong here - but I have the following card and I'd be able to beep it out.
Would that help your efforts or is this the wrong one (it is working in my SE/30 so I might be completely wrong)?

post-1953-0-36222700-1487718211_thumb.jpg

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OMG!!!!!! That's the ONE!  [:D]]'>  Yes, if you could buzz the connections from those two chips to wherever they go it would be a tremendous help! THX ever so much for joining the fray!

 

How can that card work in an SE/30? Do you have it installed in the PDS passthru of another card?

Edited by Trash80toHP_Mini

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Glad to be of help! I'll try to buzz them asap, for the time being here are the images I shot over the years, maybe you can go ahead and lookup the chips to begin with: https://goo.gl/photos/Bdw1Sa4gCgm9jcF76

 

As for why this works in my SE/30: I honestly don't know - I acquired the card at about the same time as my Turbo but that was merely a coincidence (nevertheless a very happy one).

It works both, connected directly to the PDS slot in the SE/30 and through the Asante PDS-Passthrough.

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How does it possibly fit into the SE/30 slot? Is the opening in your chassis much longer than usual so that you can plug it directly into the PDS? That CoPro socket section should interfere with the chassis?

 

 

 

edit: just checked your pics, I can't wait to throw them into my Illustrator file, it looks like exactly the same card layout I was working from in developing the pinout diagram! [:)]]'>

Edited by Trash80toHP_Mini

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It is and I'm very pleased to hear it functions correctly in the SE/30.

 

Played a bit in Illustrator and the card's PCB seems identical the the one in the scans over in the NuBus Mafia collection on 'fritter. That's what I snagged as my template. I've now got off's pictures set up in layers in a new rev of my visual schematic. The only differences I can see are that the pads for the smaller 20pin IC and the CoPro Socket are populated.

 

I wonder if the card works fine in the IIsi with just the larger 28pin PAL(GAL?) on board? Maybe the SE/30 requires both? Dunno, we'll get it figured out eventually!

 

off, would you like to work from my Illustrator diagrams looking at the PCB from the solder side or the component side? I'll rough in the control pins/signals for all three slots. I'll keep Data, Addressing, Power, Ground etc. in invisible layers so you won't need to test quite so many possible connections. [:)]]'>

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Yes, the illustrator file would be much appreciated!

If possible (don't have Illustrator at hand), I'd love something that either Sketch can edit (SVG?) or that I can print (read: PDF) and write on.

 

Regarding "does it fit the SE/30 case": Nope, it does not. Not without the Asante Ethernetcard anyways.

Even then, it's a very, very instable sandwich and honestly: If anything, this project would be the perfect solution to my problem (read: diy board with a layout that would better fit the SE/30).

I know the Stratos is out there - but why not do it yourself? ;)

 

As a final note, I was able to figure out what chips there are on the board: It seems both of them are PALs, the bigger one being a TI PAL20L8 and the smaller one being a TI PAL16L8.

Once the layout if figured out, I guess we can also figure out a way to dump these - from what I can see in the docs there is no memory and as such every programmed function can not rely on any internal state. Might be mistaken on that, but we can go into details later on. I should have everything at hand to make up a dumping tool, but that is for later as well :)

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That's what I thought was going on physically with your card, had to be. Strange that there are versions floating about with either one or two PAL configurations. I'm off tomorrow, so I'll get more in on the AI8 file and I can always export it in .pdf for your markup.

 

It's funny you mentioning reading the PALs on your board. I'm assuming all have had their security fuses blown, so I'm in the beginning stages of setting up an Orange pi ONE to brute force all the possible I/O combinations out of each and every one of the little bat rastards I can lay my grubby little paws upon. So far I've got 'em for two other adapters I still need to depopulate and scan.

 

I fugure you'll be wanting to "see" the graphic from the component side. I usually look at 'em from the solder side, it's way faster to buzz the connections from that side, but heck to keep in contact with the source pin. If you've got rows of header pins it's probably easier to plug 'em into the connectors and buzz from the top. I'll give that a look see, I just got a bunch of long header/socket pairs in from China.

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Oh - sorry for plainly ignoring your actual question: Yes, component side would be awesome!

I have some actual 120pin PDS connectors so I'll use them to buzz.

 

Regarding the PALs: that's pretty much what I thought of doing - i.e. brute-force all input connections (should be 2^10=1024 for the 16L8 and 2^14=16.384 for the 20L8) and then mapping out the logic diagram for the PAL. But again, let's get to that when the connections are laid out.

 

I'm hoping to do the actual buzzing tomorrow, but might be Saturday until I finish. If you have any pdfs to share until then I'm very eager to use them. Thanks in advance!

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I tried to get as much done as possible in order to not be of no use to you today (EST here or tonight EuroTime?) so here's what I've got:

 

Whole PCB w/Key

post-902-0-65262200-1487963351_thumb.jpg

 

25pin PAL Detail

post-902-0-86161800-1487963368_thumb.jpg

 

28pin PAL Detail

post-902-0-06324400-1487963392_thumb.jpg

 

If you PM me a realmail address I can attach a PDF, Illustrator 8 (OS9) file with layers a/o an EPS Export (dunno about the layering) or whatever I can do to help. I hope this board layout view isn't too confusing, it's the best way I've found to document the 3D model of a board as I see it developing in my head.

 

Looks like a lot of signals are held high, dunno what that adds in terms of trace buzzing complications? I hope it's clear how the traces pass through the resistors/whatever and continue on to make connections.

 

It might be a good idea to verify what I've documented first, then clear up what's partially obscured (pink) on the two PCBs and then move on to the balance of the board. As you verify the layout, I can knock the color coding back to grayscale for what's good to go in the overview and dump each color coded set of traces for each signal into its own layer for detailed examination.

 

Does that sound like a plan?

 

Happy hunting! :rambo:

 

 

 

 

edit: forgot to mention the pink pads on PAL28, those are the pins that look like they aren't connected to anything. Doesn't make sense, I'd think they'd be held high or pulled low if NC?

Edited by Trash80toHP_Mini

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LOL! Here's another one for this go-round showing one more obscured trace I put into the latest file and the "Peripherally Involved?" traces/pads layer not included in the PDF?

 

post-902-0-25597000-1487968867_thumb.jpg

 

 

How'd the attachments work out? I'm wasted for the time being! :blink:

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Well - that was fun :) You did pretty much most of the hard work; I have merely put my multimeter to good use and verified most of your connections.

Unfortunately, what you can do in Illustrator, I can't even dream of - so here is my version, about 99% finished (except for 5 pins on the 20L8 everything is mapped out and mostly verified).

 

Please forgive my colouring everything, if that doesn't make sense to you. It's pretty simple, really - every connector (MB, PDS, CI) has its color, every row (A,B,C) has its own shade.

Obviously this dictated name: 120 Shades of Pins

 

Hopefully I can finish the missing pins tomorrow, if not maybe you can figure them out. I fear, though, that this would require desoldering the chip as I cannot come up with a way to find the traces otherwise.

PowerCache 120 Shades of Pins.pdf

Edited by off

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LOL! Now I get to do some hard work translating your tables into something visual so that I can understand it! My head doesn't grok tables or conventional schematics. :-/

 

There's a resounding silence in here  .  .  .  hopefully someone else will jump in to help flesh this stuff out so everyone can understand it?

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I was doing some housekeeping and found a boo boo. While adding individual pin designations for each connector and correcting the number of positions on one of them, I noticed I had a connection I'd put in that was very different from what's obvious on you sticker-free board.

 

post-902-0-74094400-1488036770_thumb.jpg

 

The correction is obviously shown in bold. ;D

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