Nothing ever seems to be happenin' over at fritter, and the MAF *I think I finally figured that one out!* is a little hard to take after hanging out here. I'm pretty sure somebody is hoodwinking the finder with phantom RAM at startup, but confirmation from somebody who knows is really slow in coming *I gave 'em the freakin' pinouts fer cryi........* if it's ever coming at all. The copy for the ebay ad seems....carefully .....crafted? Something bothers me about it anyway.

jt ;-)

There isn't any RAM on that board (which is probably why they mention that it is so much smaller than a Dove memory upgrade board), I wonder what the illegible markings were/are on the third chip. I've only seen one (it was a production run item) other board that had markings sanded off the IC packages. This instance be might just be bad lighting/photography. I doubt it......creative.....deceptive..........maybe more like it.

jt

welcome sage, just be glad it wasn't a freakin' EPROM!

at first i thought you were talking about me but there's no way i'll ever get any credibility back in this joint, heck they'll probably laugh me out of the fritter forums after this......

I agree with you for the most part, but I think this guy knows exactly how he's misrepresenting somebody's high school hack. Reread the copy, it's too well crafted, this thing doesn't work and he's skating very close to the edge of frau...

My latest embarassment at fritter:
*ok, let's try for the longest post on record on a second forum!*

I wonder if (since memory was $$$$$$, back in the day!) Apple used an oddball lot (cheap/available) of chips on this mobo or if sombody did the 128k-512k upgrade with peculiar RAM, anybody got something layin' around for comparison?

There isn't any RAM on that board (which is probably why they mention that it is so much smaller than a Dove memory upgrade board), I wonder what the illegible markings were/are on the third chip. I've only seen one, non-mac short production run, board with the markings sanded off the IC packages (to discourage casual reverse engineering, which works much better with pictures, btw!). This instance might just be bad lighting/photography. I doubt it ...... creative..... deceptive .......... maybe. At 500% in GraphicConverter it sure looks like retouchin' not Jpeg'n artifacts on the mystery chip to me, same thing seems to have been done to the blank areas on other IC's (so the blank one doesn't look completely out of place?).

Parts on the "prototype" (hack?):

Jumper wires (fugly, amateurish job) across D & /CAS pins of (512k config of memory with peculiar characteristics) 256x1 DRAM tied by (much too heavy) jumper wires leading to "memory board with no memory on it".  /Ras leg directly tied on one bank of DRAM and another jumper wire looks like it's tied to a via next to the SIP on the other bank of RAM....dunno

•••••

radio-shack lookin' project board

•••••

Mystery 16 pin DIP IC

•••••

10 pin SIP that looks like a resistor pack.....dunno

•••••

CN74F74-X REV 1A0
MICROCIRCUIT DATA SHEET

DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP

General Description

The  F74 is a dual D-type flip-flop with Direct Clear and Set inputs and complementary (Q/Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse.  Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse.  After the Clock Pulse Input threshold voltage has been passed, the Data inputs is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input.

Asynchronous Inputs:
LOW Input to Sd sets Q to HIGH level
LOW Input to Cd sets Q to LOW level
Clear and Set are Independent of clock
Simultaneous LOW on Cd and Sd makes both Q and Q HIGH

•••••                      

DM74LS32
Quad 2-Input OR Gates

General Description

This device contains four independent gates each of which performs the logic OR function.

•••••

Looks like something might be flip-floppin-in-n-out thru gates: 4 discrete signals? 2 signals each to/from 3 pins on each bank of DRAM IC's that just happen to have interesting capabilities. Something is triggered just before/after some (address cycle on each bank of memory?) signal...somewhere.

I smell fish, was curious enough to do some leg work, but nobody with real TTL  expertise has jumped in to........

LITTLE HELP PLEASE!
tia
jt

p.s. even if I'm way off the mark, the curiosity is killin' me and I'd like to know, 'sides my skin is plenty thick!  

p.p.s. I'd REALLY like to see how well that extra 512k of memory performs, or the first 512k for that matter.

p.p.p.s. my kid tells me I never know when to stop! *......nah!.. *

1. The mod ("prototype" circuit board hack) is a hardware memory multiplexer.
2. The ROMs tell this FatMac to check out the two rows of 256x1 DRAM as usual....
3. They're set up to run through the entire address space envisioned by the designers...
4. My guesstimate of their design limit assumptions at the time were for 4 banks of 256x1, which is why the Dove memory expansion card that is mentioned was a functional upgrade.
5. This particular FatMac/128k mobo was upgraded with 256x1 DRAM "Nibble" IC's capable of a 4 stage multiplexed address space (for reasons as yet undetermined).
6. The control lines of the first two (physically present) rows of DRAM are addressed (the equivalent of Bank A on a Plus), after which the ROMS tell the mobo to check for the next two rows of DRAM (not present on this rev, they'll be implemented on the Plus's mobo as the SIMM sockets in Bank B)
7. Some clown (this guy I like!) realizes the implications of the config. or creates it (even sneakier, still ok in my book.)
8. Builds a simple physical multiplexer for the "Nibble" DRAM IC rows and installs it (wild hack, I really love it!)
9. Somewhere during the RAM check at startup an address register shift triggers the mod circuit to flip a gate setting which changes the address space response of Bank A (2 rows/half banks of 256x1 DRAM =2.256k SIMMs) to that of Bank B.
10. The mobo polls the address space of the as yet unimplemented Bank B, reading Bank A a second time and reports 1 Meg of RAM to the Finder.
10. Somewhere at the end of the Bank B address space memory check, a register shift flops the gate setting back the way it was at startup and it stays there until the next request for memory in the address space of Bank B.
11. The clown makes sure that his boot disk has Finder Rev. 5.3 on it , which dutifully reports 1024k of RAM on its splash screen.
12. The FatMac is still fully functional because this particular Finder Rev. hasn't got a freakin clue as to how to ask for an address in the space that will become Bank B on the Plus.
13. The clown unloads this hack because he needs space for something that's interesting to a younger generation of hackers.
14. Somebody gets taken thereafter, somewhere, sometime, or maybe decides to pass the novelty 1024k/512k on to the next.......
15. If the guy with the ebay auction running had 10% of the wit and sense of humor of my theoretical clown (who I would like to think is somewhere laughing so hard he's in serious danger of internal injuries).......
16. the Auction End Date (or the delivery of merchandise?) would coincidentally be April 1.

All of the above is sheer conjecture and a matter of personal opinion, based on obvious oversimplifications of...........
Something is either the funniest gag hack I've ever encountered..........or I'm absolutely clueless!
jt

my kid already thinks the latter btw.
My head hurts again.........wrists too! and on this forum i can say that it may be a great gag and I'm still clueless, but you guys know me, so......

Since no TTL guys have jumped in, could somebody at least let me know if my assumptions regarding Finder 5.3 have any basis in reality.

Nebulous "backup" info pasted below, conclusions above are inferred from very remotely related multiplexed memory scheme in a wildly different application.

And just in case a TTL/CMOS boffin is waiting to (pounce) assist!
[fixed]
41256
+---\/---+
1 -|A8 gnd|- 16
2 -|Din /CAS|- 15
3 -|/WR Dout|- 14
4 -|/RAS A6|- 13
5 -|A0 A3|- 12
6 -|A2 A4|- 11
7 -|A1 A5|- 10
8 -|Vcc A7|- 9
+--------+

7474
+---\/---+
1 -|/R1 Vcc|- 14
2 -|D1 /R2|- 13
3 -|CP1 D2|- 12
4 -|/S1 CP2|- 11
5 -|Q1 /S2|- 10
6 -|/Q1 Q2|- 9
7 -|gnd /Q2|- 8
+--------+

7432
+---\/---+
1 -|1A Vcc|- 14
2 -|1B 4A|- 13
3 -|1Y 4B|- 12
4 -|2A 4Y|- 11
5 -|2B 3A|- 10
6 -|2Y 3B|- 9
7 -|gnd 3Y|- 8
+--------+
[/fixed]

--==========================================================--5.3
EXTERNAL MULTIPLEXER CODE
The multiplexer core logic is developed to address 4MB memory composed of two 1Mx16 bit
DRAM modules - as illustrated earlier in Table 2. The code is quite simple, however, there is
a requirement of 31 external I/O signals.
--====================================================
MODULE << amux >>
-- Description : Address MUX for 1Mx16x2 DRAM
--====================================================--library
ieee;
use ieee.std_logic_1164.all;
entity amux is
port(
LA : in std_logic_vector (21 downto 2);
AMuxCas : in std_ulogic;
MA : out std_ulogic_vector (9 downto 0)
);
end amux;
architecture behavior of amux is
signal LAi : std_ulogic_vector (21 downto 2);
signal AMuxCasi: std_ulogic;
begin•LAi <= To_StdUlogicVector(LA);
AMuxCasi <= To_X01(AMuxCas);
process(LAi)
begin
if (AMuxCasi='1') then
MA <= LAi(11 downto 2); -- col address
else
MA <= LAi(21 downto 12); -- row address
end if;
end process;
end behavior;
6. Synthesis
The protocol conversion code can be sysnthesized into a 32 macrocell CPLD (CY7C371i), using WARP TM synthesis compiler, from Cypress Semiconductor. Table 3 demonstrate the utilization of resources within the CPLD. The address multiplexer code can also be synthesized into a similar CPLD. Although the amout of macrocell utilization would be quite low but notice that there is a requirement of 31 I/O pins for the multiplexer. Alternatively, both protocol convertion and multiplexer codes may be compiled into a larger 64 macrocell CPLD or integrated with existing FPGAs in the system.
7. Conclusion
Detailed interfacing and implementation issues between V360EPC (or V292PBC) from V3 Semiconductor and PPC403GC from IBM were described. V360EPC provides an efficient and cost-effective solution for interfacing PPC403GC processor to the PCI bus. Higher performance PPC403GCX series may also be interfaced in the same fasion since the external bus interface is the same - internal 2x clock and 8x cache. The protocol conversion circuitry has been described in great details and can be easily realized within a conventional 32-macrocell CPLD.

Edited by - Trash80toG-4 on 05 Feb 2002 10:35:29

Where the heck do you learn these things??

I suppose that's a downfall of my being an English major...

As an English major you should recognize fiction!

jt
=8-}

* remember....keep.. it....? .. short......! ...* *sigh*

Does anybody know anything about Finder Rev 5.3?

Which System Rev. was other half of which OS Combo??
Released when?
Supported which Macs?
Addressed how much memory?
Replaced by which Finder/System combo?
Released when?
Supported which Macs?
Addressed how much memory?

tia
jt
=8-}

back again, just realized I never did post a direct link to the freakin' reason for this thread!
http://cgi.ebay.ca/aw-cgi/eBayISAPI.dll?ViewItem&item=1328274474

What is the copyright date on the 512k's ROMs? anybody got some or a mobo handy, I'm gonna go rummage thru the boxes for the ROMs I pulled off in the ke upgrade I did.

Pretty sure the ROM says '85 in the 'peg on ebay.
Does anybody recognize a/o know of a code for 64/128k differentiation in the 'peg, I've only worked w/EPROMS.

I'm beginning to wonder if the SCSI connector on this "prototype" is really (still) functional.

Is there a table of ROM versions/dates/cpu model/feature support available? Link please!

tia
jt