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Q605/LC475 (onboard) ram upgrade.
- Thread starter uniserver
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Absolutely, this post is great and I much appreciate everything you've post about memory and everything else. The information you've posted has been the inspiration for at least three of my projects.
I try to assimilate whatever you, bbraun, bmow and now comrade bear post about anything and everything! :approve:
many thanks to all of you,
jt
I try to assimilate whatever you, bbraun, bmow and now comrade bear post about anything and everything! :approve:
many thanks to all of you,
jt
Do the Q605/LC 475 boot w/o the DRAM on the MoBo?
From what trag has said about the limitations of the second SIMM in the 605 and the 630, it makes me wonder if the Mobo RAM is excised these machines might be able to address the full theoretical loadout using the four full capabilities of double banked SIMMs. It appears to me that the MoBo RAM is set up as a hobbled replacement for the first(second?) bank of the extra SIMM and that doing away with the MoBo DRAM ICs might free up those control lines for use on the unaddressable bank of the additional SIMM?
It's still and "under the board" PCB Hack, but what the heck!?! [}
] ]'>
From what trag has said about the limitations of the second SIMM in the 605 and the 630, it makes me wonder if the Mobo RAM is excised these machines might be able to address the full theoretical loadout using the four full capabilities of double banked SIMMs. It appears to me that the MoBo RAM is set up as a hobbled replacement for the first(second?) bank of the extra SIMM and that doing away with the MoBo DRAM ICs might free up those control lines for use on the unaddressable bank of the additional SIMM?
It's still and "under the board" PCB Hack, but what the heck!?! [}
] ]'>jt has the right of it.Do the Q605/LC 475 boot w/o the DRAM on the MoBo?
From what trag has said about the limitations of the second SIMM in the 605 and the 630, it makes me wonder if the Mobo RAM is excised these machines might be able to address the full theoretical loadout using the four full capabilities of double banked SIMMs. It appears to me that the MoBo RAM is set up as a hobbled replacement for the first(second?) bank of the extra SIMM and that doing away with the MoBo DRAM ICs might free up those control lines for use on the unaddressable bank of the additional SIMM?
It's still and "under the board" PCB Hack, but what the heck!?! [}
If you absolutely want to stick to chips which will fit in the 20 pin spots already on the logic boards, then yes, you are limited to 4MB total.
However, if you are willing to rig up additional connections, then you should be able to go up to 64 MB or possibly more. But this will be messy with wires and/or additional boards involved.
Case re-opened! From the bottom side. }
Continue discussion here if you would: Memory Addressing Questions
I'm already hip deep into the memory addressing issues of the IIsi, so I may as well head toward the deeper end of the pool and take on the Quadras 605 & 630 while I'm at it.
Great news, it turns out that only the Data lines are buffered by the 74LS245 quartet in order to buffer the Vampire VRAM/DRAM in Bank A.
We're getting there . . .
[attachment=0]l16kram.jpg[/attachment]
:?:
:?:
There's a fine old tradition of increasing memory capacity by piggybacking chips on each others backs like that. What the image doesn't show at first glance, is that it is not just a matter of soldering all the pins together, one to one. One must also get the additional higher address pin and apply some digital magic to some of the control lines to make it work. If you just piggyback directly, you simply have two chips trying to do identical work. They need a way of knowing that one set is used when an address pin that they can't see (not enough address pins) is '0' and the other is used when that address pin is '1'.
That said, it greatly reduces the amount of extra wiring, because most of the address pins, and all of the data pins are shared.
However, on the gripping hand, figuring out which control signals to modify can be a bear. You can't just hook up OE_ because that only handles reads. You can't assume that you can just modify RAS_ because the machine might use CAS before RAS refreshes, and that would mess with those. Without knowing the basics of how the machine is accessing RAM for both refresh and read/write operations, it gets tricky. I think that if you modify OE_ and WE_ both, then it should always work, but I'm not 100% certain about that.
That said, it greatly reduces the amount of extra wiring, because most of the address pins, and all of the data pins are shared.
However, on the gripping hand, figuring out which control signals to modify can be a bear. You can't just hook up OE_ because that only handles reads. You can't assume that you can just modify RAS_ because the machine might use CAS before RAS refreshes, and that would mess with those. Without knowing the basics of how the machine is accessing RAM for both refresh and read/write operations, it gets tricky. I think that if you modify OE_ and WE_ both, then it should always work, but I'm not 100% certain about that.
I didn't have time to post more than the pic before work today. You can see where one of the legs of the piggybacked IC is not connected to the matching leg of the lower IC if you look closely.
My thought is to look for a "double sided" 8MB 30-pin SIMM that has eight chips on each side of the type you're successfully using to net 4MB onto the MoBo.
Reverse engineer the addressing and control lines of such a SIMM will likely yield the information that will allow you to do the ugly Piggybacked RAM thing with some degree of confidence that it will work as an 8MB (onboard) RAM upgrade.
Putting a memory daughtercard underneath the MoBo is a far more elegant solution, capable of achieving vastly increased memory for very little money and less tedious wirework.
I've been watching this thread with great interest. I would love to double the amount of RAM my 475 can handle... 8-o
Sorry to hijack this thread a bit, but would this sort of thing work for a Classic II? It has 2MB onboard in the same style as this. Any chance it could be increased to 8MB (meaning 16MB total with the SIMM slots)?
Sorry to hijack this thread a bit, but would this sort of thing work for a Classic II? It has 2MB onboard in the same style as this. Any chance it could be increased to 8MB (meaning 16MB total with the SIMM slots)?
Perhaps the Classic II is a different enough design to the Classic (I) to allow more than 2MB onboard RAM.
The Classic II is based on the LC II architecture (I think), so it stands to reason that the same limitations apply (both the C II and LC II are limited to 10 MB of RAM, for example).
Or maybe that was the Color Classic?
c
EDIT: No, I was right. According to Wikipedia, the Classic II architecture closely resembles that of the LC/LC II, and as such is subject to the same limitations and architectural design flaws.
Or maybe that was the Color Classic?
c
EDIT: No, I was right. According to Wikipedia, the Classic II architecture closely resembles that of the LC/LC II, and as such is subject to the same limitations and architectural design flaws.
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I spent an hour or more downloading all the crap I could find relevant to this issue . . . for the morning. |)
A few highlights:
Dunno if this is the proper arrangement for the systems we're trying to hack, but to these crossed eyes it looks pretty good.
A couple of roads best left untraveled:
Step one:
dsc_0281.jpg[/attachment]
A few highlights:
Dunno if this is the proper arrangement for the systems we're trying to hack, but to these crossed eyes it looks pretty good.
A couple of roads best left untraveled:
Step one:
dsc_0281.jpg[/attachment]
Adding to my question regarding the Classic II, I just looked at a high res logic board image (since I'm too lazy to open mine) and it looks like it only has 4 RAM chips. Going by the part number shown (KM44C1000AJ- 8) it is unfortunately already using 1M x 4 ICs (which would make sense since it has 2MB(x8) onboard RAM).
Still, I wonder if it would get a speed boost using something faster than 80ns chips. The datasheets I found listed 70ns as an option for AJ, 60ns for the BJ revision, and up to 50ns for the DJ revision.
Those might also speed up the IIsi/475 as well.
Still, I wonder if it would get a speed boost using something faster than 80ns chips. The datasheets I found listed 70ns as an option for AJ, 60ns for the BJ revision, and up to 50ns for the DJ revision.
Those might also speed up the IIsi/475 as well.
