Hmm, I don't remember the details of that now, but for most purposes I don't think it's essential to get an exact clock speed match for the original hardware, as long as it's pretty close. Yeah, those internal clock dividers are somewhat limited as to what frequencies they can do, so if you really need exactly 15.6672 MHz or whatever, you'll need to use an external oscillator to get it. What's more important than the exact clock speed is the relative speed of the various clocks, as you said. If all the clocks are ultimately derived from the same master clock, then you shouldn't have issues with edge synchronization.
It's been a few years since I looked at it, but I think one of the problems with Plus Too was that it was pushing the flash ROM to the edge of its timing specs, and I didn't understand the synthesis software well enough to set up proper timing constraints for the ROM access. I suspect it was occasionally fetching a bad value from ROM, causing the instability problems I observed. I never really figured out a good way to debug problems like that - I could debug functional problems like a reasoning error in the design, but not timing or electrical problems.
It's been a few years since I looked at it, but I think one of the problems with Plus Too was that it was pushing the flash ROM to the edge of its timing specs, and I didn't understand the synthesis software well enough to set up proper timing constraints for the ROM access. I suspect it was occasionally fetching a bad value from ROM, causing the instability problems I observed. I never really figured out a good way to debug problems like that - I could debug functional problems like a reasoning error in the design, but not timing or electrical problems.
