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MicroMac Performer Redux: Cloning a 68030 Accelerator for Compact Macs
- Thread starter Trash80toHP_Mini
- Start date
Noted, all components are labeled in the "Coloring Book" line buzzing pics I've posted. I'll add those labels into the AI file in the next update. I've yet to get the all my scribblings doinked into the Illustrations.
Remember that Bolle and I are reverse engineering very different Accelerators, so don't get the data intermixed. :blink:
h34r:
Remember that Bolle and I are reverse engineering very different Accelerators, so don't get the data intermixed. :blink:
They're the same GAL in SMT as the DIP version that fell victim to joethezombie attack. Fuses be damned, but registration(?) is a concern. Saving cost and power are good, saving PCB real estate for more and better goodies to be tacked on in the future is paramount!
h34r:
Well then welcome aboard! But leave that 68000 be! The SE can almost certainly use the 68000 interface, but the Plus definitely doesn't speak SE PDS. I've already got an invisible connector for the SE PDS on the right side of the board just about where it is on the actual Performer. [
] We'll likely get the board worked out to use either way, only the Classic is out of luck for now.edit, now that I think of it, the 68030 should be placed on the left side of the GALs for a more proper representation of the accelerator. That way the signals that pass over the GAL pins for sampling, disappear into the GALs for them to do their magic and the signals generated in or tweaked by the GALs show a natural flow through the schematic.
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You're getting far ahead of the program with concerns about generic address/data buss. You don't want anything cluttering the schematic that's 1:1 until the differences are nailed to the wall for very close inspection. Right now it's about the GALs and nothing but the GALs! [
]
Once the continuity testing and documentation of these deviations from the bus are is finished the real work begins with the logic probe. IIRC that having a general understanding of function cuts the brute force attack on the function of a GAL.
In the meantime there here's a project for 1:1 connections that you could sink your teeth into. It would appear that the QFP packaged SMT 68030 appears more abundantly available, in less demand and so are much less expensive than the PGA package.
Agena Shield could make logic probing a snap. Obviously I won't be ordering any SMT GAL Sockets.
For Code Names we're going with NASA nomenclature. [}]
] Once the continuity testing and documentation of these deviations from the bus are is finished the real work begins with the logic probe. IIRC that having a general understanding of function cuts the brute force attack on the function of a GAL.
In the meantime there here's a project for 1:1 connections that you could sink your teeth into. It would appear that the QFP packaged SMT 68030 appears more abundantly available, in less demand and so are much less expensive than the PGA package.
Agena Shield could make logic probing a snap. Obviously I won't be ordering any SMT GAL Sockets.
For Code Names we're going with NASA nomenclature. [}
]
Nope, per the Agena diagram, we'll definitely be using PGA for 68030 and GAL sockets on the prototype. SMT 68030 goes on the Agena Shield at 1:1 with the BGA board interconnect/logic probe header thruholes on the Agena/Prototype assembly.
edit: LOL! Forgot component labels again! Also forgot the block diagram for the schematic:
[68030] <- [GAL] - [GAL] - [GAL] - [GAL] - [GAL] <- [68000]
edit: LOL! Forgot component labels again! Also forgot the block diagram for the schematic:
[68030] <- [GAL] - [GAL] - [GAL] - [GAL] - [GAL] <- [68000]
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I can't afford a Logic Analyzer or the time to use one, so I've got a side project for a Pi DIO expert:
It would be a huge help to have a DIO monitoring shield mounted between the Prototype and Agena. Given enough DIO lines, all interboard connections could be output for display in a window that mimics LEDs on the schematic. But we don't need any of the 1:1 connections analyzed, that cuts complexity/DIO line requirements drastically.
Somebody has probably done most or all of it already in the PiVerse? On the off chance they haven't, doing it as a general purpose logic analyzer with Mac Accelerator tendencies would be a great hacking tool to have kicking around the Verse.
Eudi, I know you're out there too, what do you think of that notion for a logic analyzer? I need a voice of reason in this thread, you're it again, bud! [
]
It would be a huge help to have a DIO monitoring shield mounted between the Prototype and Agena. Given enough DIO lines, all interboard connections could be output for display in a window that mimics LEDs on the schematic. But we don't need any of the 1:1 connections analyzed, that cuts complexity/DIO line requirements drastically.
Somebody has probably done most or all of it already in the PiVerse? On the off chance they haven't, doing it as a general purpose logic analyzer with Mac Accelerator tendencies would be a great hacking tool to have kicking around the Verse.
Eudi, I know you're out there too, what do you think of that notion for a logic analyzer? I need a voice of reason in this thread, you're it again, bud! [
]
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Finished up p.3 of the coloring book last night and may have discovered a couple of important logical operations in the GAL maelstrom:
View attachment 21503
This is the kind of information we'll need in the "working version" of the schematic for analysis unobstructed by 1:1 bus connections. []
I'm putting each control signal into its own layer in the AI file. The four Address lines I've found to be monitored by the Gals will be on one layer.
View attachment 21503
This is the kind of information we'll need in the "working version" of the schematic for analysis unobstructed by 1:1 bus connections. [
] I'm putting each control signal into its own layer in the AI file. The four Address lines I've found to be monitored by the Gals will be on one layer.
Sorry if my comms are disjointed/unclear. I'm juggling a lot of bowling pins in my head and learning to read, much less create a traditional schematic is far into the future. PP,4-5 of the GAL Coloring Book need to be completed before anything else has practical value.
Speaking of which:
Speaking of which:
Rev 2 with corrected names and the bus moved out of the way. Eagle has a 68881, but not a 68882, so I may have to make one. Ugh.
View attachment Rev 2 Netlist.txt
View attachment Rev 2 Netlist.txt
Looks great!
Is the pinout all that much different in the DIP package?
Is the pinout all that much different in the DIP package?
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My bad, I somehow read that as 68010 for 68000. The Gals go into PLCC-20 thruhole sockets. I have a tube of 36 on the way as of right now. []
I'll try to dig up the datasheet for the drill pattern if I haven't already got it on file. It's a basic three all around with an inset square of two to a side for a standard 100mil spaced array. It was a very common part, though not nearly as common as the SMT version apparently.
If there were room for 5 pairs of DIP GAL thruholes I'd have gone that route and put my precious five in DIP adapters, but these will be less crowded on the 10x10 square.
] I'll try to dig up the datasheet for the drill pattern if I haven't already got it on file. It's a basic three all around with an inset square of two to a side for a standard 100mil spaced array. It was a very common part, though not nearly as common as the SMT version apparently.
If there were room for 5 pairs of DIP GAL thruholes I'd have gone that route and put my precious five in DIP adapters, but these will be less crowded on the 10x10 square.
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All in good time, "reading" the GALs to determine if they're fused or registered is still pretty far off.
First I'm socketing the CPU and the Crystal Can for the 32MHz test to see if this project is really worth the fuss. This is the bottom of three tiers, lowest cost Accelerator in MicroMac's lineup for the Compacts.. The GAL ICs functions just fine on 50MHz PowerCache Accelerators, so I expect them to shine when I clock the board for the 40MHz IIfx Processor test.h34r:
I need to order a set of SMT PLCC-20 Sockets to install on my performer for use when the time comes to desolder my quintet.
Even if they're registered, the logical operations will be apparent enough. Bolle has collected a lot of info on formulas for interfacing the 68030 to the 68000. Unlike Trekkers, we're treading where the Amiga fanatics have gone before! []
First I'm socketing the CPU and the Crystal Can for the 32MHz test to see if this project is really worth the fuss. This is the bottom of three tiers, lowest cost Accelerator in MicroMac's lineup for the Compacts.. The GAL ICs functions just fine on 50MHz PowerCache Accelerators, so I expect them to shine when I clock the board for the 40MHz IIfx Processor test.
h34r: I need to order a set of SMT PLCC-20 Sockets to install on my performer for use when the time comes to desolder my quintet.
Even if they're registered, the logical operations will be apparent enough. Bolle has collected a lot of info on formulas for interfacing the 68030 to the 68000. Unlike Trekkers, we're treading where the Amiga fanatics have gone before! [
]
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I'm taking a second run at explaining what the "Agena Shield" does.
I've illustrated a dual purpose combination SMT Pad/Thruhole footprint that allows either type PLCC Socket to be installed (hopefully) on Prototype or the QFP 68030 Agena Shield.
A DIP strip socket/tall header board interconnect system for mounting Shield to Prototype also provides headers for attaching leads of Logic Analyzer. Same for the BGA socket/tall header setup, the headers plugged into the PGA 68030 Socket correspond 1:1 (crosses fingers) with the pads of the QFP 68030.
A nice overhead shot of the SMT Socket with a size reference floated to the surface of the 'Bay, so I dragged it on board. Gotta find a nice Pic of the PGA socket, that gradient thing was an accident I left alone.
Does anyone have a link to a REAL PostScript PDF data sheet for the QFP 68030? I need to snag the outlines and text for use in AI. Same for the PGA IC pinout. I HATE scanned in paper page images, they're awful.
Unifying the Killy Klip/68000 leg interface with a Right Angle SE PDS Connector installed puts Agena vertical for easy probing The "NuBus" type connector is far more robust with additional power/ground lines, buffering and some strange voltages and clocks thrown in there too!
The cutout necessary for SIMM Socket clearance make use of the setup in the horizontal impractical. It's gonna be open air testing on the bench for a while.
That's the plan anyway. I've got two more pages to go in the GAL Coloring Book and a bit of GAL rearranging in the AI file to relax between connection buzzing sessions. I'm running on empty ATM, but I've got three days to rest up at work! []
I've illustrated a dual purpose combination SMT Pad/Thruhole footprint that allows either type PLCC Socket to be installed (hopefully) on Prototype or the QFP 68030 Agena Shield.
A DIP strip socket/tall header board interconnect system for mounting Shield to Prototype also provides headers for attaching leads of Logic Analyzer. Same for the BGA socket/tall header setup, the headers plugged into the PGA 68030 Socket correspond 1:1 (crosses fingers) with the pads of the QFP 68030.
A nice overhead shot of the SMT Socket with a size reference floated to the surface of the 'Bay, so I dragged it on board. Gotta find a nice Pic of the PGA socket, that gradient thing was an accident I left alone.
Does anyone have a link to a REAL PostScript PDF data sheet for the QFP 68030? I need to snag the outlines and text for use in AI. Same for the PGA IC pinout. I HATE scanned in paper page images, they're awful.
Unifying the Killy Klip/68000 leg interface with a Right Angle SE PDS Connector installed puts Agena vertical for easy probing The "NuBus" type connector is far more robust with additional power/ground lines, buffering and some strange voltages and clocks thrown in there too!
The cutout necessary for SIMM Socket clearance make use of the setup in the horizontal impractical. It's gonna be open air testing on the bench for a while.
That's the plan anyway. I've got two more pages to go in the GAL Coloring Book and a bit of GAL rearranging in the AI file to relax between connection buzzing sessions. I'm running on empty ATM, but I've got three days to rest up at work! [
]
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Here are some of the descriptions on pics I searched. I'll unearth DCaDftMF for what Apple called it in the spec if this isn't enough
ksm Row 3 Male 96 pin Din 41612 Euro type
96P Plug R Type Vertical Euro DIN 41612 Connector Male ...
VME Bus DIN Connector Mechanical Drawing, Board Connector ...
Looks like the SMT 68030 has four more pins than the PGA 68030. Are they redundant power and ground pins in your schematic capture models? Comparing pinouts between types looks like a major PITA!
ksm Row 3 Male 96 pin Din 41612 Euro type
96P Plug R Type Vertical Euro DIN 41612 Connector Male ...
VME Bus DIN Connector Mechanical Drawing, Board Connector ...
Looks like the SMT 68030 has four more pins than the PGA 68030. Are they redundant power and ground pins in your schematic capture models? Comparing pinouts between types looks like a major PITA!
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