Diagnosing Macintosh Classic

[LaPorta]

At this point, it’s always possible that some of the RAM itself is bad, not the connections to it.

 

[musawir]

At this point, it’s always possible that some of the RAM itself is bad, not the connections to it.

But I should be able to get to the sad mac icon as before, no? it feels to me more like a severed net issue, but i can't pin point where

 

[musawir]

Did a bunch of probing. Log of some checks and probes below, but working theory at this point is that the CPU is executing and doing bus cycles. The failure seems to be some write cycle not making it through, where /AS stays low and /DTACK is not asserted. Any hints would be appreciated!

CPU findings:

• 68000 reset is not stuck. /RESET is high.
• 68000 /HALT is high.
• CPU clock is present.
• 68000 /AS on pin 6 pulses normally, but periodically it goes low and stays low briefly, then returns to normal pulsing. This pattern repeats.
• 68000 /DTACK on pin 10 pulses normally, but during the /AS stuck-low interval, /DTACK goes/stays high. Since /DTACK is active-low, this means the CPU is waiting for a bus acknowledge that is not arriving for that specific access?
• 68000 /BERR on pin 24 appears high; no bus-error abort was observed.
• 68000 R/W on pin 9 goes low during the /AS stuck-low interval, so the stuck cycle is a write.
• 68000 /UDS pin 7 goes low during the stuck cycle.
• 68000 /LDS pin 8 goes low during the stuck cycle.
• 68000 /VPA pin 23 was later observed pulsing all the time.
• 68000 /VMA pin 21 pulses normally, then goes high during the bad period.

RAM findings (chips are Samsung KM44C256AJ-10 DRAMs):

• RAM /WE pin 3 stays high throughout.
• RAM /RAS pin 4 pulses normally, but goes high during the /AS stuck-low period.
• RAM /CAS pin 17 was hard to probe and the reading was uncertain; it seemed like it might keep pulsing.
• Since /RAS and /WE are high during the stuck cycle, the stuck write does not appear to be an onboard DRAM write.

ROM findings:

• ROM pin 22 appeared to pulse, and at one point seemed to go low during the /AS stuck-low interval.
• ROM pin 24 /OE seemed high all the time.
• ROM pin 23 seemed to pulse normally, then low during /AS low.
• ROM pin 20 had a fuzzy pulse normally, then low during /AS low.
• Later, ROM pin 22 was rechecked and seemed to continue pulsing all the time, so the earlier “ROM selected during stuck write” may have been a bad read on my part, or maybe this read is bad
• The CPU address lines A23 pin 50 and A22 pin 51 were probed and both pulse normally, then go high during the stuck cycle.

UH6 findings:

• UH6 pin 1 /CLR is high all the time, so the chip is not being held cleared.
• UH6 pin 9 CLK pulses all the time.
• UH6 pin 10 / Q4 pulses normally, then goes low during the stuck cycle.
• UH6 pin 11 / D4 pulses normally, then goes low, matching Q4 behavior.
• UH6 pins 12 and 15 not connected/unused.
• UH6 pin 2 / Q1 steady pulse.
• No adjacent shorts were found between UH6 pin pairs

UH6 to CA5 continuity map confirmed:

• UH6 pin 2 / Q1 -> CA5 pin 21
• UH6 pin 5 / Q2 -> CA5 pin 3
• UH6 pin 7 / Q3 -> CA5 pin 4
• UH6 pin 10 / Q4 -> CA5 pin 25