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Sorry, yes, I meant 1 transaction at a time.

Dev notes say the CPU bus runs at a 37.5MHz, but it doesn't say how fast the '040 bus runs. Various contributors here have said maybe there's an extra wait state to take it down to 33MHz. Yet I'm sure I've seen a document on how '040 bus transactions work. Maybe it was on the '040 document...

@Phipli : I checked the compiler options for my Code Warrior Gold 11 (Academic) to see how they differ from yours. And indeed there are fewer options: As you can see, only the PPC601, 603 and 604 were supported at the time (I picked it up in late 1996), not the 603e, 604e and 750. This is one...

It turns out I have a sonic PcCard ethernet adapter that should work with my PB1400c too. I'll try it and provide an update!

https://68kmla.org/bb/threads/fantasy-m88100-macs.46869/post-525482 Indeed. So, on a 6100, video is in DRAM. So, that means that area of DRAM gets marked as non-cacheable. On a 6200, the frame buffer is 1MB of DRAM behind Valkyrie, which can store up to 4x transactions. So, to properly resolve...

( @Phipli ) it adds up, but there are a few reasons why I don't think that's the cause. Firstly, there are no Read-Modify-Write memory instructions on a PowerPC, just load and store. So, this sequence of bus cycles in non-cached DRAM would have to be implemented in software, not the Capella...