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At most 5 if using a pseudo-slot design and the 20 MHz half-speed clock, as there's only 6 slot area in the memory map ($9 to $E inclusive). Using 'slow space' ($6 area) you can use the 20 MHz clock without interfering with the NuBus area. It makes the software abit more complex, but the...

The NuBusFPGA should definitely work in there. Well, now that your IIsiFPGA is working in a IIsi and a SE/30, it might be time to try a bitstream for the IIfx as well :-) I was worried the weird PDS implementation might cause issue, but it is working for the SEthernet/30, so worth a shot...

It was introduced in late '98 if MacTech is to be believed. But clearly for PowerMacs, I wonder if they would work on a 68k Mac... I'm surprised anyone still created NuBus device as late as that (says the guy that did one in 2022...). I'll be content with the first Highly Desirable Macintosh...

Well, I'll be a pedant and claim the QuadraFPGA is the third time, following the NuBusFPGA and IIsiFPGA at first and second :) Although they are similar enough that they can probably all be counted as one and just want all three medals 'cause I'm greedy :) More seriously, I don't remember any...

Any pointers to the relevant documentation? There DeclROM isn't particularly well documented post-DCDMF3 and I can't find an explicit documentation of the Display Manager, let alone the ROM part of it. (... some more googling...) Apparently, from Develop 25 (March '96), you need the "Display...

I'll try and post something later this week (if @Jockelill doesn't beat me to it ;-) ), but it's somewhat frustrating: MacOS (8.1 at least) seems to auto-generate the names in the list, so if you have the same resolution twice (once windowboxed, once 'hardware') then you get the same name twice...

No, the reset system needed between resolution / depth change isn't reliable and I haven't figured out why yet... so it still a matter of re-changing resolution/depth to force a reset :-(

Just forgot to update the public thread with the new status, nothing new vs. the ones you tested some weeks ago :-) They are in the repo as (a) 'LitexPHY' and (b) 'AltPHY'.

Update on that: this particular limitation has been (somewhat) lifted. The QuadraFPGA (and NuBusFPGA, IIsiFPGA) now has the choice of two different Highly Desirable Macintosh Interface PHY (the part that generate the appropriate signals to the connector): (a) the Litex-style one (written in...

Beware the orientation of the '882, they will fit in the PLCC socket even the wrong way... the socket should have some indication where pin 1 is supposed to go (in a PLCC package it will be in a middle of a side, not in a angle). Interesting. It suggests the NuBus implementation Radius did...

Hehe, seems you're already working on it :-) Fragment of schematics like this might help understand, but are too limited for recreation by a third-party like myself. For instance, take U28. It has an OE signal that doesn't appear anywhere else (that I can see), so is that driven externally or...

Those ACT16651 are apparently still current, but Mouser doesn't stock them, they're not cheap, and MOQ is 80. '651 or '648 are probably a cheaper option. For cost reason, you really want all your SMD components on one side if someone like JLCPCB is to assemble them. I would recommend first...

Having so much weight off-center is probably not very good for the DIN connector. I should add some support. But as a prototype, it does the job :-) Not surprised, so is QuickDraw on such machines. 68030 were very nice in their days, but they aren't fast by any modern standard... BTW, in my...

Indeed, you can generate the required 10 MHz 75% duty cycle of NuBus by just 'masking in' every other low pulse of the 20 MHz 50% duty cycle CPU clock, giving you a fixed phase relationship between the two. If Radius exploited that (and it seems likely they did), then I agree it would be much...

Neat. Did anyone trace the board as well? If it is running half-clock just to avoid the cost of an extra clock, then it's an easy fix. If it's somehow requiring the clock to have some relationships in the GAL/PAL, then it will be harder to 'fix'. But in either case, with the appropriate...

Has anyone seen one of those? Do they have chips on the back or just the front? Looking at it again (prompted by this thread), it only has six 8-bits transceiver chips instead of the expected eight. There's also more ALS240 than in Apple's implementation, so maybe a slightly different bus...

The socket is very likely to be for a PLCC '882, as that is a common feature of IIsi adapter and it is the appropriate one in the picture (68 pins). Other than that, the front side is using six 74ALS648 as bus transceiver. Apple used eight74ALS651 in their discrete implementation (before...

Well, that raised some interesting questions... first here is the assembled contraption: Home-made dual-PDS adapter w/ PGA FPU (20 MHz '882 here) at the back (upside-down). IIsiFPGA on the 'normal' slot (bottom). IIsiSEthernet in the middle, with a micro-to-mini USB cable to power the MacSD...

TL;DR: I now can mount my 'netatalk' share on my IIsi via Ethernet :) Well, I had the parts :-) Once I could program the CPLD and had soldered all the parts on a board that looked completely OK, still had to figure out why I couldn't program the ROM. I had optimized my routing on the PCB by...

Excellent news. So it should work on mine at 20 MHz. That and the ethernet/rom selection, but as that's just combinatorial from apparently working addresses, I also guessed it was the clock. With your opinion concurring, I spent some time trying to figure out the problem - and somehow figuring...