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That's a rather big project. As for TSOP.... eek! I guess paste, mask and a heat gun or oven is the only way to reliably do those. Far easier to do that on a new board without any other components on there.
What caps are you using? Those are smaller than the ones I could see on RS... but there...
Thanks for the link, very interesting, especially the capacitor part. I may need to add a couple to the circuit, or use the one provided on the main circuit board provided for the VSLI chip.
The SIOC-24 SMD 74HC154 chips are currently available from both of the UK chip suppliers, both the Nexperia and TI versions are ~66p + sales tax.
It's also available as a TSSOP part.
Actually there was a 74AC154 made by Hitachi, which is spec sheet I was getting the timings from. (Best: 7ns, Typical: 9ns, Worst: 11ns) I guess that they didn't bother continuing as circuits would have to assume the worst case, which is only 3ns faster than the HC part and that guarantees 14ns...
The 154 is available in plentiful supply from multiple manufacturers and from multiple suppliers. Yes, the AC part is no-longer available but electrically it looks no different to the HC part and the timing change is small (in this context). Having thought about it, both the GAL and the 154 are...
Looking at the spec sheets, there's not a lot of difference between the timing of the 74AC154 and 74HC154 in the worst case. The AC part has a transmission time of between 7ns and 11ns, with 9ns being typical. The HC has a guaranteed 14ns. Removing the 244 would more than compensate for this...
I've just checked Farnell, I can get the HCT parts for both the 244 and 154 easily, so that's probably the way to go (rather than mixed LS/HC). That should negate the need for pull-ups at all.
It'll be a 74HC154 (there's just not a symbol for that in the KiCad database, but they're pin compatible). I'd still need to pull up the output from the 244 into the 154 as that's TTL -> CMOS (according to what I've read this is required).
By the way, I'd like to say that I really...
It was a "belt and braces" approach and probably not needed but seeing as it's trivial to add to the schematic I thought I'd add it. I could just not fit the resistor array after all and see if it works. If it doesn't that I can easily solder the component on the board, which I couldn't if the...
The 154 I can get is the HC version (SIOC package). It's recommended that you use a pull-up between the output of an LS or AC part and an HC one, from what I've read.
As for SYS_POWER*, the 154 has two enable pins and both have to be low to allow any of the output to be pulled low, so putting...
I realised I'd miscounted the number of inputs (should be 8 ) after I modified the schematic, so yes a 16V8 will work fine.
As for the 74HC154 they seem to be plentiful from both RS Components and Farnell, but only as SOIC packages.
As for SYS_POWER*, from what I can make out from the...
Actually a GAL is a good idea. It's need a 20V10 for the number of inputs.
It'll still need the 244 and the pull-ups but should put everything else into the GAL, making a three chip solution to the problem.
There's no DTACK coming to the card so the timing must be being controlled by the GLUE chip. I wonder how the RAM card is supposed to signal when the data is valid on the data bus. Or is the GLUE assuming that it will be ready after N-cycles?
Given that SRAM chips take longer for the data to...
Here's the first draft of the address decode circuit. Looking into the problem, it might be best to replace all the other functionality as well. I'd replace the chip with a PLCC-44 socket and fit a daughter board using a Wilmslow 9303 adapter.
Actually, I think I can use a 74xx240 to do all the upper address line decoding.
Connect _E0 to ground, connect A21, A22 and A23 to I0, I1 and I2. Connect _O0, _O1 and _O2 to I3 and the _O3 output to _E1. Then connect A20 to I4. The _O4 signal can then be used to directly control _E1 on the...
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