Recent content by dougg3

Not dumb at all! I’ve just spent more time than I care to admit troubleshooting multiple LC IIIs. You make a good point, a trace to the onboard VRAM could also be bad

The LC III doesn't require a VRAM SIMM.

I’d normally agree with you, but I saw it with my own eyes on my LC III. Usually bad RAM results in a chime followed by the chimes of death.

I have an LC III that had this exact same symptom (chime and then nothing) and it ended up being a broken trace (well, a bad via) between the CPU and the RAM on the data bus. It was like the RAM test was failing so badly that the Chimes of Death couldn't play. If the adapter you're testing works...

The ROM socket is 64-pin, not 68-pin, so I wouldn't expect it to be compatible for those. Even if you cleverly hacked it to remove 2 pins on each side, I'm assuming the peg locations would be wrong and it wouldn't hold the ROM SIMM in its latched position properly.

I bought some of these on eBay a while back and can confirm that if you cut them apart into single sockets, they are exactly identical to the original VRAM socket that was mounted on my Performa/LC 550 board.

They are. They go to A20 and A21. I haven't tried it myself, but it should work. I'm not sure if you would need to do any MMU reconfig like what was required for the Quadras, but it should be possible to get 4 MB of ROM in the LC III.

Back to the original problem of my IIsi power supply always turning itself back on when I try to shut it off: The original PSU that I saw this problem on is still dead. I've struggled a bit with motivation to fix it after experiencing a couple of MOSFET explosions while testing out more replica...

Thanks for that kind offer @Callan! I’d say let’s hold off for now, but I will definitely take you up on it later. I found a small bug yesterday and I want to make a version 4 (maybe with some additional tests) before I ask for a bunch of re-tests.

I was super curious if your prototype's EASC chip would behave any differently, but honestly I think it's the same. I'm guessing that it's occasionally normal for that second interrupt to happen. Thanks again for testing that! I'm trying to document Apple Sound Chip behavior on every 68k Mac...

Thanks! I appreciate it! Interestingly enough, the weird anomaly I noticed on your first test didn't happen during this test. The extra unknown IRQ in the first test was probably a "FIFO A half empty" IRQ firing without FIFO B showing up as half empty.

Awesome, thank you! And I agree! With the quicker write to FIFO B, your SE/30 responds just like my IIci, so everything is making sense.

Thank you! Out of curiosity, would you mind running this version on it too? Your test showed one small peculiarity I’m interested in. https://github.com/dougg3/ASCTester/tree/se30_testing

Ha! It’ll be its own operating system by the time I’m done with it. :D

@Callan Tired of my requests yet? :-) I made one more improvement to the SE/30 testing branch, forcing the FIFO writes to A and B to be back-to-back. I'm curious if this eliminates (or at least minimizes) the extra IRQs. Same test link again: https://github.com/dougg3/ASCTester/tree/se30_testing...