Futura II NuBus -> 030 PDS conversion . . .

[Trash80toHP_Mini]

.  .  .  has become my current obsession.

Since my project to hack the IIsi NuBus Adapter onto the PDS appears to require bus mastering expertise I'm not likely to acquire, removing the NuBus MUX and to dumb a card back down to I/O bus spec seems the best way to approach this.

Target is the SE/30's 68030 socket and  I've got both ThinNet and 10bT daughtercards for my pair of Futura's, so that's an added bonus if I can grab the brass ring.

Looks like the wedge would be the pads for the output side of theoe two SMT MUX ICs.

lowencmac:

The card provides standard QuickDraw acceleration and supports the following resolution/color combinations:

• 640 x 480 up to 24-bit
• 832 x 624 up to 24-bit
• 1024 x 768 (at 75 Hz) up to 8-bit

E-Machines Futura cards have a rotary switch for setting the resolution. The following is a list of switch settings. This setting is overridden when using a supported monitor with Apple's sense coding.

resolution refresh monitors
1 832 x 624 67 Hz T16
2 1024 x 808 71 Hz T19/TX
3 640 x 480 60 Hz any VGA
4 1024 x 768 60 Hz any XVGA
5 832 x 624 75 Hz T16a-E16
6 1024 x 768 75 Hz E16, SuperMac 19", others
7 640 x 480 67 Hz E16, others
8 1024 x 768 75 Hz RasterOps 19", others
C 13"/16" Dual Resolution E16
D 16"/19" Dual Resolution T16II/E16
E 19"/21" Dual Resolution T19II
F 16"/21" Dual Resolution T16II

I've got a 10" color CRT headed into the extra SE/30 case sometime soon. The monitor supports the two resolutions in bold. Removing the A/B and possibly the Original equipment PSU sheet metal surround for the ATX PSU conversion makes for area/cubic requirements for the monitor's guts.

Barring complications elsewhere, pulling the Video ROM may free up onboard video's PseudoSlot $E interrupt for the card. It definitely makes the Video Subsystem on that interrupt disappear from Slot Manager's watchful eye.

Yeah, I know about the CRT neck length thing, but I cheat really neat. [}] ]'>

 

[Trash80toHP_Mini]

Hit my first roadblock already! [] ]'>

The 74fct16245t is a general purpose bus to bus transceiver, which means decoding the multiplexed NuBus addressing/data signals would be implemented in the big ASIC above them.

Question now is: will TI's pair of NuBus transceiver chips work between the 68030 and the NuBus connector without the help/interference of the matching NuBus Controller IC setting it up as a clocked, multislot NuBus implementation?

Boils down to building a single NuBus card adapter for the 68030 socket with a NuBus connector that adds up to a torqued PDS card.

 

[Trash80toHP_Mini]

I'm right back to looking at docs for the NuBus Chipset from the DuoDock!

SN74ACT2440 NuBus Interface Controller

SN74BCT2420 Address/Data Transceivers and Registers (16bit 2 required)

Can't do without the controller, but it looks like the complexity of the interface can be cut way back..No need for bus mastering or multiple slot implementation. Hopefully the chipset can be dumbed down to a level that it might be interpreted by the SE/30 as a single non-mastering NuBus card with DeclROM support. Bus mastering is the root of all NuBus evil for the SE/30.

Time to curl up with the DCaDftMF docs on NuBus implementation . . . again. :

 

[Trash80toHP_Mini]

GRRR! This mess appears to be morphing back into the earlier quest to build a custom NuBus adapter for the SE/30 based on the DuoDock1's discrete NuBus off PDS implementation. A slave only implementation of TI's NuBus controller seems to be the path to the yellow brick road. Thankfully the Contoller and Transceivers on the Dock1 board are thoroughly documented as well as the signals on the Duo's docking connector.

Has anyone ever seen a schematic for the Dock1 or the Duo 210/230? I've got notes on the PBX bus bridge of the 2300c to work from, but a real schematic from either side of the docking connector for any Duo or Dock would be striking gold.

 

[Trash80toHP_Mini]

Time to start a dedicated thread again, meanwhile:

First step will be buzzing connections from the Docking Connector to the Controller IC to verify inputs. Address/Data lines are a direct mapping between Docking Connector and Transceivers.

Listing of control signals present on Duo Docking Connector available to NuBus Controller:

/STERM - 9 /STERM Synchronous termination

/DS - 10 /DS Data strobe

/AS - 11 /AS Address strobe

/HALT - 13 /HALT Halt

/BERR - 14 /BERR Bus error

/BGACK - 15 /BGACK Bus grant acknowledge

SIZ1 - 41 SIZ[1] Transfer size bit 1

SIZ0 - 117 SIZ[0] Transfer size bit 0

/SCC IRQ - 62 /SCC IRQ SCC interrupt request

/CBREQ - 86 /CBREQ Cache burst request

/DSACK1 - 87 /DSACK1 Data size acknowledge bit 1

/DSACK0 - 88 /DSACK0 Data size acknowledge bit 0

/BR - 89 /BR Bus request

/BG - 90 /BG Bus grant

FC1 - 92 FC[1] Function code bit 1

FC0 - 93 FC[0] Function code bit 0

/RMC - 94 /RMC Read-modify-write cycle

/R/W - 116 RD Read/Write

/CPURESET - 96 /CPURESET CPU reset (bus invalid)

/IO RESET - 140 /IO RESET Reset output to I/O systems

IOCLK - 40 IOCLK 15.6672 MHz I/O clock

CPUCLK - 95 CPUCLK CPU bus clock

/SLOT E IRQ - 138 /SLOT E IRQ Pseudo-NuBus expansion slot E interrupt

Schematic of NuBus of TI Controller-Transceiver Chipset

http://pinouts.ru/visual/gen/duodock.jpg