On a less silly note: the DATA/Addressing lines aren't made all THAT much longer to make timing an issue for the SIMMspender hack.
I don't know, you might be surprised. Once you get into the low-mid double-digit Mhz speed ranges is where you start seeing motherboard designers doing things like waving traces around to make sure that all the wires leading to a memory device are the same length. My guess is you'd *probably* get away with an inch or two of slop, but it's not kosher.
Mechanically the thing would be something of a nightmare in any case. You can't really make assumptions about how the SIMM slots are laid out on the host motherboard so the whole thing would have to be flexible. (30 pin SIMM sockets come in both vertical and slanted varieties, the socket-to-socket spacings vary, etc.)
Since many of the signals are exposed on the top and bottom layers on the MoBo and on the SIMMs, why is shielding for the CAS/RAS lines above board so important?
Someone might correct me, but I don't think you'd need the CAS/RAS lines from more than one socket, or at least the full set of them. You will need the 8 data lines, and you *might* need the strobes. However... taking a brief look at the pinouts of the two types of SIMMs and an operational description of how the two work, something tells me that there are gotchyas to this that might require putting some active components on the adapter for refresh to work correctly, at least if the 72 pin SIMMs used in such an adapter were made using components denser than those used on a 30 pin SIMM 1/4 of the size. IE, if a machine like a Quadra 950 supports 16 MB chips with only 2 [or 3, ignore the third] chips that's 8 chips for 64MB. If you were to install a 64MB SIMM using *less* than 8 chips in your SIMM-adapting nightmare adapter the logical layout of the chips might require a different refresh cycle than the memory controller in the host machine can supply. In particular I suspect this problem would crop up with 72 pin SIMMs that use 8 or 16 bit wide DRAMs.
Dual-rank 72 pin SIMMs would also be difficult to use without help. So an adapter like this would have significant operational gotchyas.
(There's an old thread on this board where the question is brought up why some machines will only work with the 8/9 pin versions of a given size SIMM, not the 2/3 chip version. The answer is that the wider DRAMs sometimes require more refresh cycles than the memory controller on a given machine can supply. Coincidentally this was brought to my attention recently when researching ways to upgrade an old TRS-80 Color Computer 3 from 128k to 512k. The obvious way, replacing the four 4464 DRAM chips with four 44256s, doesn't work because the denser chips require a 512 cycle refresh while the counter built into the GIME DRAM controller only counts to 256. So in order to get 512k you have to add a satellite board made up of 41256 chips that accept the 256 cycle refresh.)