2-chip/3-chip 1MB RAM sticks in a Macintosh SE?

[8bitbubsy]

Some sources (even Apple themselves) say that you can't use 1MB 2-chip RAM SIMMs in a Macintosh SE, while other sources (random forum posts) may suggest that it does work. Have anyone confirmed if 2-chip/3-chip 1MB RAM SIMMs work (or don't work) in a Macintosh SE?

Macintosh SE: Technical Specifications - Apple Support

support.apple.com

"This system cannot use two-chip 1MB SIMMs."

 

[Phipli]

Some sources (even Apple themselves) say that you can't use 1MB 2-chip RAM SIMMs in a Macintosh SE, while other sources (random forum posts) may suggest that it does work. Have anyone confirmed if 2-chip/3-chip 1MB RAM SIMMs work (or don't work) in a Macintosh SE?

Macintosh SE: Technical Specifications - Apple Support

support.apple.com

"This system cannot use two-chip 1MB SIMMs."

Basically the reason people tell you to buy 8 chip simms for the SE is because most / all of them work.

2 chip SIMMs are hit and miss. Some work, some don't. If you have some, try them, if you are looking at buying some... check the return policy.

 

[JC8080]

I have successfully used 2 chip 1mb SIMMs in a Plus, though I'm not sure if that relates at all to SE compatibility.

 

[ymk]

The Plus, SE and Classic depend on video access to refresh RAM and this covers the first 512 rows.

2 chip SIMMs have more than 512 rows and those extra rows won't be refreshed in these machines.

The computer might appear to boot fine, then crash after you use it for a while.

 

[8bitbubsy]

Alright, good to know!

 

[JC8080]

The Plus, SE and Classic depend on video access to refresh RAM and this covers the first 512 rows.

2 chip SIMMs have more than 512 rows and those extra rows won't be refreshed in these machines.

The computer might appear to boot fine, then crash after you use it for a while.

I just did some testing and can confirm this. I was skeptical since my Plus and SE both seem to work fine with 4x 2-chip 1mb SIMMs, but I have never used either extensively with those SIMMs. I put the 2-chip SIMMs in my SE. Everything seemed fine, I ran Speedometer 3.06 and did the full battery of tests. Everything was fine until the very end of the test. After it finished the math tests, right before it beeps and says tests complete, the program crashed. I did this five times, and every time it crashed at exactly the same spot. I put the 8-chip SIMMs back in and checked, the test completed fine every time. I put the 2-chip SIMMs back in, and I get the crash every time. I put the 8-chip SIMMs back in for one final test, and the test completed without issues.

The interesting thing is everything else works fine. I ran multiple loops of Apple Personal Diagnostics and Snooper with no issues. I set After Dark to random modules cycling every 30 seconds and let that run for 30 min or so with no issues.

It's possible you could use a machine with 2-chip SIMMs for casual stuff and never run into a problem, but it does appear there are certain scenarios where they will not work correctly.

 

[ymk]

The interesting thing is everything else works fine. I ran multiple loops of Apple Personal Diagnostics and Snooper with no issues. I set After Dark to random modules cycling every 30 seconds and let that run for 30 min or so with no issues.

Any data written to those rows will rot unless accessed regularly (which benchmarks and After Dark likely do).

File writes are at serious risk of corruption.

This might be fixed with an extension that reads a word from a certain number of rows on vertical retrace.

Assuming a 62.5ms / 16Hz row refresh rate and and 1024-row SIMMs, (512*16)/60 = 136.53 reads per vertical retrace.

I'd guess it would cost around 2% CPU time.

 

[8bitbubsy]

Does this also apply for the Mobius 030 accelerator for Macintosh SE? I put some 2-chip RAM in that.

 

[Phipli]

It isn't just as simple as 2 chip vs 8 chip. Its a case of  some 2 chip SIMMs cause issues.

My SE has been running stable with 4x 2 chip SIMMs since about 1995. But I would always recommend buying 8 chip SIMMs to ensure a greater chance of compatibility.

People shouldn't be saying that because one set of 2 chip SIMM didn't work, they all don't work. If you already own said two chip SIMMs, there is no reason not to try them. Just give them a good test.

 

[8bitbubsy]

Well, 4x 2-chip 1MB seems stable so far when installed on the Mobius 030.

 

[ymk]

It isn't just as simple as 2 chip vs 8 chip. Its a case of  some 2 chip SIMMs cause issues.

Look up the IC on your SIMMs. If they have more than 512 rows, you're taking a risk.

 

[Phipli]

Look up the IC on your SIMMs. If they have more than 512 rows, you're taking a risk.

30 years.
30.
Thirty years of stable use.

 

[ymk]

30 years.
30.
Thirty years of stable use.

Well, how many rows then?

 

[Phipli]

Well, how many rows then?

I presume the right number

 

[GRudolf94]

That doesn't make sense. You don't get weird numbers of rows per memory device like that in such old devices. Memory arrays are symmetrical, or square, call it whatever you want. If you have 512 row addresses, and 512 column addresses, you have a total 256k (well, 262144) addresses. To the Mac, it makes no difference if those are organized in two devices where each address holds four bits, or eight devices where each address holds one bit each. Also, were it the case that row count was an issue, no SIMM having more than 512 rows would ever work, regardless of internal organization. Again, that would limit an SE to accepting only 256kB SIMMs. (512 rows=2^9 row addresses=A0-A8=no device larger than 256k).
Furthermore, anyone riddle me this: why is it a Classic, built on the exact same BBU guts as the SE, comes populated with four banks of 256k*4 DRAM devices, equivalent to four two-chip SIMMs?

 

[ymk]

That doesn't make sense. You don't get weird numbers of rows per memory device like that in such old devices. Memory arrays are symmetrical, or square, call it whatever you want. If you have 512 row addresses, and 512 column addresses, you have a total 256k (well, 262144) addresses. To the Mac, it makes no difference if those are organized in two devices where each address holds four bits, or eight devices where each address holds one bit each. Also, were it the case that row count was an issue, no SIMM having more than 512 rows would ever work, regardless of internal organization. Again, that would limit an SE to accepting only 256kB SIMMs. (512 rows=2^9 row addresses=A0-A8=no device larger than 256k).
Furthermore, anyone riddle me this: why is it a Classic, built on the exact same BBU guts as the SE, comes populated with four banks of 256k*4 DRAM devices, equivalent to four two-chip SIMMs?

My Classic has eight M5M44256BJ-8 on the riser board.

Each chip is:
512 rows * 512 columns * 1/2 byte width = 131072 bytes (128KB)

 

[Phipli]

My Classic has eight M5M44256BJ-8 on the riser board.

Each chip is:
512 rows * 512 columns * 1/2 byte width = 131072 bytes (128KB)

But the computer's interface to that is an 8bit wide data bus with 10 address lines to give 1024 rows, and 1024 columns... exactly the same as my 2 chip SIMM?

 

[GRudolf94]

Each chip is:
512 rows * 512 columns * 1/2 byte width = 131072 bytes (128KB)

Correct - that's what 256k*4 means. 262144 positions addressed via 9 address lines (2^9 cols x 2^9 lines) with 4 bits each. With two chips making up a full byte, you get 256kB. 4 times those two chips equate the 1MB on the riser, the same as on the LB, the same as four SIMMs making up two banks of one word each.

@Phipli the Classic expansion i'face is also 2x (or 3x?) word-wide banks capable of 1MB each (so the same as two two-chip 30-pin SIMMs), with the first (other) two banks being the soldered 1MB on the board, and with one of the banks on the official Apple card being the soldered-down 8x 44256, but correct other than that.

In any case, if the Classic is perfectly happy running *4 DRAM 512cols and up, it doesn't make sense that the SE wouldn't, and that is probably chalked up to a timing violation of some sort.

 

[GRudolf94]

Correction, making sense of the organization on the riser: the soldered 1MB is two banks of 512kB each, with one spare bank on SIMM slots. There's 3 pairs of CAS low/high signals going to it, and each bank can only be 512kB or 2MB.

 

[ymk]

You're right that with a square layout, 1024 rows are needed for 1MB SIMMS.

8/9-chip 1MB SIMMs must also have 1024 rows. Considering that, Apple's explanation is a bit puzzling:

A few machines, namely the Macintosh Plus, Macintosh SE, and Macintosh Classic, depend on video accesses to refresh all of their DRAM. As the video circuitry accesses sequential locationsthrough the video frame buffer, it simultaneously refreshes row after row of memory, eventually refreshing all 512 rows. Memory at the 4 Mbit density, however, is arranged as 1024 rows andthere are not sufficient video accesses to refresh all 1024 rows. Chunks of memory simply goblank. Thus for a different reason, 4 Mbit DRAM parts are also not compatible with these olderMacintosh hardware designs.

https://www.tech-insider.org/mac/research/acrobat/9204.pdf

The only other plausible explanation in there I could find is that 4Mb chips introduced a JEDEC test mode that gets tripped on Mac IIs, but nothing is mentioned about the SE.