Try wiring a through hole ceramic capacitor over the power pins on chips in the area. Perhaps you're modifying the capacitance on chips with the IPA. Perhaps there are broken traces to decoupling capacitors.Ive narowed it down to UD16.. it boots and works fine if i put iso on and around UD16.. weird. Otherwise it just does bad chime and no video. Its not the cooling effect cos I tried freezer spray and no joy. UD16 is the SRAM connected to the serial asic.
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A couple around the serial asic.. looked fine but the via was not doing its job due to battery spill rot.Good progress. Out of curiosity which traces did you have to repair?
Thanks.. That's what I love about this forum.. ☺some great folks on here.Watching your progress and cheering you on! Also no surprise Mr. IIfx @joshc is here helping out as he has with my new IIfx journey.
Hah! I’d be happy to explain in more depth, but we should probably start another thread for that discussion. Great troubleshooting @SophieRose!So I only understood maybe half of the above, but you blew my mind @mdeverhart !
Okeydokey cheers @mdeverhartHah! I’d be happy to explain in more depth, but we should probably start another thread for that discussion. Great troubleshooting @SophieRose!
Also check continuity between pins 27 of the SRAM and 71 of the ASIC if you haven't already. If that trace is broken, pin 27 is floating and can cause trouble by registering low.I took these readings..
Yeah did that.. it's a straight connection.. only other thing I can think of doing is lifting pin 71 of the asic and seeing what the resistance is then between the pin and gnd and the now unoccupied trace n gnd just to confirm.. but i recon the asic is at fault here.Also check continuity between pins 27 of the SRAM and 71 of the ASIC if you haven't already. If that trace is broken, pin 27 is floating and can cause trouble by registering low.
Thanks but I'm good for now, just enjoying watching from the sidelines as you all put on quite a technical show.(I'll Google how latching works, sounds interesting). I never studied computing at these levels, appreciating the opportunity to expand my knowledge. Keep going team!Hah! I’d be happy to explain in more depth, but we should probably start another thread for that discussion.
@mdeverhartHmm… resistance measurements don’t look too bad. I’m not sure what normal would be, but for a partial short I’d expect something < 100 Ohms. For comparison, can you measure the resistance between /OE (pin 22) and 5V and between /OE and GND?
Lifting pin 71 on the ASIC to isolate might be a good intermediate step, but given the resistance measurements I’m not sure it’s necessary yet.
Was there any capacitor leakage in the area? Is the /WE trace routed straight from the ASIC to the SRAM on the top layer, or does it go through any vias?