The "820-0961-A" mystery G3 3.3V FlashRom

[croissantking]

Here's to hoping, having USB and Firewire on one card would be great. Limited room in those things.

Those card works fine, afaik - it’s the one that additionally has SATA onboard that allegedly has problems.

 

[joevt]

It looks like it is, but I can’t see any new features or behaviour having run it for a little while in my G3.

ChatGPT says:

This line sets the cache line size for PCI-PCI bridges during configuration. It was likely added in Rev D to ensure proper initialization, enhance performance, or fix compatibility issues with specific devices.

A user of a rev C ROM Beige G3 reports that applying the cache line size and master latency timer fix that exists in the rev D ROM for PCI bridges improves performance.

You can test this on a Beige G3 or any Power Mac.

First, find the config address of the PCI bridge that contains the controllers (SATA, USB, FireWire, etc.) that you want to test/improve.

dev pci/pci-bridge
.properties

Result:

reg                     00006000 00000000 00000000  00000000 00000000

Look at the reg property. You want the non-zero address that ends in 00 which in the above example is 6000.

Now go to the PCI host device that is the parent of the PCI bridge to read the PCI config registers. Offset 0 is the device and vendor IDs. offset 0xC is the cache line size and the master latency timer.

dev pci
\ get the vendor and device IDs and verify that they match those of the PCI bridge.
6000 config-l@ 8 u.r

\ get the cache line size and the master latency timer.
600c config-l@ 8 u.r

Result:

00012008

In this example, the cache line size is 0x08 and the master latency timer is 0x20. 0x01 is the PCI header type (0x01 = PCI bridge).

To change the cache line size and the master latency timer, use this:

0000 600c config-l! \ set cache line size and master latency timer to 0.

or this:

2008 600c config-l! \ set cache line size to 32 and master latency timer to 8.

Then continue booting into Mac OS and run some benchmarks. You'll want to run benchmarks for 0000 and 2008. I wonder if other values can be used?

Could it have possibly been a fix for the Rev C incompatibility with the Sonnet Tango Trio?

Probably not. I did find an issue with PCI controllers that don't have a PCI Option ROM with Open Firmware fcode (USB and FireWire controllers). I made a patch to fix this which I added to the ROM extender that I mentioned at
https://68kmla.org/bb/threads/mathey-msata-13umac-ide-sata-card.47740/page-5#post-578415

I've attached the updated version. The source directory has a list of patches. The one discussed here are:
create-defaults patches.of
pci-pci-config-patches.of

 

[croissantking]

A user of a rev C ROM Beige G3 reports that applying the cache line size and master latency timer fix that exists in the rev D ROM for PCI bridges improves performance.

Good to know. I only have one multifunction card, a USB 2.0/Firewire, it has a bridge chip on it. It would be easy for me to benchmark throughput as I can just swap out the ROMs between reboots.