Hello all,
At last, the IIsiFPGA's smaller sibling is here: the IIsiA7 Mini. It's basically the same thing (the Highly Desirable Macintosh Interface for the IIsi), but smaller, so it shares a GitHub repo with the original version (and refers to itself as the IisiFPGA V3.0).
So, what's new? Well this time, there is no daughterboard - the FPGA is actually soldered directly on the board (and trying this was the reason for me doing the board in the first place). So
It supports the same set of options as the larger siblings in the family, with the choice of two HDMI PHY: either DVI-like with support for multiple hardware resolution (640x480 to 1920x1080 at 1/2/4/8/16/32 bpp) and windowboxing (but no audio), or closer to the better-known HDMI, 1920x1080 hardware resolution only (at 1/2/4/8/16/32 bpp) with windowboxing and audio. There's also a PMOD connector and a serial-to-usb connector for tinkering with the gateware.
Annoyingly, I have a bug in the gateware than mistify me; the burst read from memory doesn't work despite the code working fine on the original IIsiFPGA (the new version requires an additional width converter, as the IIsiFPGA's DDR3 1:4 ratio exposes a 128-bits wide interface perfect for a '030 burst, but the DDR2 1:2 ratio exposed only a 64-bits wide interface, and that converter works fine for the acceleration engine...). Memory expansion mode works without it, but it's slower than it should be. Grr.
The original batch of IIsiA7 Mini has a slightly larger Artix-7 than the ZTex I used with the IIsiFPGA, as the 50T was cheap at time of ordering at JLCPCB - so I got that one (vs. a 35T). It's actually big enough to fit both the SQRT and DIV operator at the same time when adding my ongoing FPU project (so it has all the '040-supported FP compute instructions at in 80-bits Moto, 64-bits IEEE and 32-bits IEEE).
All the files are on the repo, as usual.
At last, the IIsiFPGA's smaller sibling is here: the IIsiA7 Mini. It's basically the same thing (the Highly Desirable Macintosh Interface for the IIsi), but smaller, so it shares a GitHub repo with the original version (and refers to itself as the IisiFPGA V3.0).
So, what's new? Well this time, there is no daughterboard - the FPGA is actually soldered directly on the board (and trying this was the reason for me doing the board in the first place). So
- It's smaller: it fits in the form factor of the IIsi adapter (but the HDMI connector isn't usable with my cables, too close to the case, so you still nee the adapter...), and it doen't have the massive thickness of the *FPGA
- It's cheaper: well, technically it is more expensive (it's a 6 layers PCB with a 256-balls Artix-7 so it ain't cheap to make even at JLCPCB), but as you don't need the FPGA daughterboard, the overall cost of the solution is (much, much) lower - less than 2/3 of the ZTex 2.12b alone!
- Requires a JTAG programmer (no onboard USB programmer, which would have raised the BoM significantly)
- Also it uses a DDR2 chip instead of DDR3, which means lower memory bandwidth but it seems ok for 1920x1080@32 bits anyway.
It supports the same set of options as the larger siblings in the family, with the choice of two HDMI PHY: either DVI-like with support for multiple hardware resolution (640x480 to 1920x1080 at 1/2/4/8/16/32 bpp) and windowboxing (but no audio), or closer to the better-known HDMI, 1920x1080 hardware resolution only (at 1/2/4/8/16/32 bpp) with windowboxing and audio. There's also a PMOD connector and a serial-to-usb connector for tinkering with the gateware.
Annoyingly, I have a bug in the gateware than mistify me; the burst read from memory doesn't work despite the code working fine on the original IIsiFPGA (the new version requires an additional width converter, as the IIsiFPGA's DDR3 1:4 ratio exposes a 128-bits wide interface perfect for a '030 burst, but the DDR2 1:2 ratio exposed only a 64-bits wide interface, and that converter works fine for the acceleration engine...). Memory expansion mode works without it, but it's slower than it should be. Grr.
The original batch of IIsiA7 Mini has a slightly larger Artix-7 than the ZTex I used with the IIsiFPGA, as the 50T was cheap at time of ordering at JLCPCB - so I got that one (vs. a 35T). It's actually big enough to fit both the SQRT and DIV operator at the same time when adding my ongoing FPU project (so it has all the '040-supported FP compute instructions at in 80-bits Moto, 64-bits IEEE and 32-bits IEEE).
All the files are on the repo, as usual.
